mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1289 from mmicko/anlogic_fixes
Anlogic fixes and optimization
This commit is contained in:
Clifford Wolf
GitHub
commit
2c8c8b3c74
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@ -1,7 +1,7 @@
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OBJS += techlibs/anlogic/synth_anlogic.o
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OBJS += techlibs/anlogic/anlogic_eqn.o
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OBJS += techlibs/anlogic/anlogic_determine_init.o
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OBJS += techlibs/anlogic/anlogic_fixcarry.o
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
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@ -1,72 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct AnlogicDetermineInitPass : public Pass {
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AnlogicDetermineInitPass() : Pass("anlogic_determine_init", "Anlogic: Determine the init value of cells") { }
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void help() YS_OVERRIDE
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{
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log("\n");
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log(" anlogic_determine_init [selection]\n");
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log("\n");
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log("Determine the init value of cells that doesn't allow unknown init value.\n");
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log("\n");
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}
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Const determine_init(Const init)
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{
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for (int i = 0; i < GetSize(init); i++) {
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if (init[i] != State::S0 && init[i] != State::S1)
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init[i] = State::S0;
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}
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return init;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ANLOGIC_DETERMINE_INIT pass (determine init value for cells).\n");
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extra_args(args, args.size(), design);
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int cnt = 0;
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for (auto module : design->selected_modules())
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{
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\EG_LOGIC_DRAM16X4")
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{
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cell->setParam("\\INIT_D0", determine_init(cell->getParam("\\INIT_D0")));
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cell->setParam("\\INIT_D1", determine_init(cell->getParam("\\INIT_D1")));
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cell->setParam("\\INIT_D2", determine_init(cell->getParam("\\INIT_D2")));
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cell->setParam("\\INIT_D3", determine_init(cell->getParam("\\INIT_D3")));
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cnt++;
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}
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}
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}
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log_header(design, "Updated %d cells with determined init value.\n", cnt);
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}
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} AnlogicDetermineInitPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,130 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static SigBit get_bit_or_zero(const SigSpec &sig)
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{
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if (GetSize(sig) == 0)
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return State::S0;
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return sig[0];
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}
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static void fix_carry_chain(Module *module)
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{
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SigMap sigmap(module);
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pool<SigBit> ci_bits;
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dict<SigBit, SigBit> mapping_bits;
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for (auto cell : module->cells())
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{
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if (cell->type == "\\AL_MAP_ADDER") {
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if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
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SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
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SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));
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if (bit_i0 == State::S0 && bit_i1== State::S0) {
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SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
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SigSpec o = cell->getPort("\\o");
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if (GetSize(o) == 2) {
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SigBit bit_o = o[0];
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ci_bits.insert(bit_ci);
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mapping_bits[bit_ci] = bit_o;
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}
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}
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}
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}
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vector<Cell*> adders_to_fix_cells;
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for (auto cell : module->cells())
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{
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if (cell->type == "\\AL_MAP_ADDER") {
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if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
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SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
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SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
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SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));
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SigBit canonical_bit = sigmap(bit_ci);
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if (!ci_bits.count(canonical_bit))
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continue;
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if (bit_i0 == State::S0 && bit_i1== State::S0)
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continue;
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adders_to_fix_cells.push_back(cell);
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log("Found %s cell named %s with invalid 'c' signal.\n", log_id(cell->type), log_id(cell));
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}
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}
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for (auto cell : adders_to_fix_cells)
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{
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SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
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SigBit canonical_bit = sigmap(bit_ci);
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auto bit = mapping_bits.at(canonical_bit);
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log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
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Cell *c = module->addCell(NEW_ID, "\\AL_MAP_ADDER");
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SigBit new_bit = module->addWire(NEW_ID);
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SigBit dummy_bit = module->addWire(NEW_ID);
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SigSpec bits;
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bits.append(dummy_bit);
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bits.append(new_bit);
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c->setParam("\\ALUTYPE", Const("ADD_CARRY"));
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c->setPort("\\a", bit);
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c->setPort("\\b", State::S0);
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c->setPort("\\c", State::S0);
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c->setPort("\\o", bits);
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cell->setPort("\\c", new_bit);
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}
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}
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struct AnlogicCarryFixPass : public Pass {
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AnlogicCarryFixPass() : Pass("anlogic_fixcarry", "Anlogic: fix carry chain") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" anlogic_fixcarry [options] [selection]\n");
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log("\n");
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log("Add Anlogic adders to fix carry chain if needed.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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break;
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}
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extra_args(args, argidx, design);
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Module *module = design->top_module();
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if (module == nullptr)
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log_cmd_error("No top module found.\n");
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fix_carry_chain(module);
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}
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} AnlogicCarryFixPass;
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PRIVATE_NAMESPACE_END
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@ -31,7 +31,10 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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output CO;
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output [Y_WIDTH-1:0] CO;
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wire CIx;
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wire [Y_WIDTH-1:0] COx;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
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@ -41,15 +44,16 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
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wire [Y_WIDTH-1:0] AA = A_buf;
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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wire [Y_WIDTH+1:0] COx;
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wire [Y_WIDTH+2:0] C = {COx, CI};
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wire [Y_WIDTH-1:0] C = { COx, CIx };
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wire dummy;
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AL_MAP_ADDER #(
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.ALUTYPE("ADD_CARRY"))
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adder_cin (
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.a(C[0]),
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.o({COx[0], dummy})
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.a(CI),
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.b(1'b0),
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.c(1'b0),
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.o({CIx, dummy})
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);
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genvar i;
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@ -59,18 +63,22 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
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) adder_i (
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.a(AA[i]),
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.b(BB[i]),
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.c(C[i+1]),
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.o({COx[i+1],Y[i]})
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.c(C[i]),
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.o({COx[i],Y[i]})
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);
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wire cout;
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AL_MAP_ADDER #(
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.ALUTYPE("ADD"))
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adder_cout (
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.a(1'b0),
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.b(1'b0),
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.c(COx[i]),
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.o({cout, CO[i]})
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);
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end: slice
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endgenerate
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/* End implementation */
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AL_MAP_ADDER #(
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.ALUTYPE("ADD"))
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adder_cout (
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.c(C[Y_WIDTH+1]),
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.o(COx[Y_WIDTH+1])
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);
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assign CO = COx[Y_WIDTH+1];
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assign X = AA ^ BB;
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/* End implementation */
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assign X = AA ^ BB;
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endmodule
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@ -154,7 +154,7 @@ struct SynthAnlogicPass : public ScriptPass
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{
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run("memory_bram -rules +/anlogic/drams.txt");
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run("techmap -map +/anlogic/drams_map.v");
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run("anlogic_determine_init");
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run("setundef -zero -params t:EG_LOGIC_DRAM16X4");
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}
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if (check_label("fine"))
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@ -186,6 +186,11 @@ struct SynthAnlogicPass : public ScriptPass
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{
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run("techmap -map +/anlogic/cells_map.v");
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run("clean");
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}
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if (check_label("map_anlogic"))
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{
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run("anlogic_fixcarry");
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run("anlogic_eqn");
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}
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