From 2c7fe42ad158a9859895399bdd876f5dbb2c7376 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 27 Mar 2019 13:47:42 +0100
Subject: [PATCH] Add "rename -output"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/cmds/rename.cc | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 466a5da53..9b1830b7b 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -24,7 +24,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name)
+static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name, bool flag_output)
 {
 	from_name = RTLIL::escape_id(from_name);
 	to_name = RTLIL::escape_id(to_name);
@@ -37,13 +37,18 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 			Wire *w = it.second;
 			log("Renaming wire %s to %s in module %s.\n", log_id(w), log_id(to_name), log_id(module));
 			module->rename(w, to_name);
-			if (w->port_id)
+			if (w->port_id || flag_output) {
+				if (flag_output)
+					w->port_output = true;
 				module->fixup_ports();
+			}
 			return;
 		}
 
 	for (auto &it : module->cells_)
 		if (it.first == from_name) {
+			if (flag_output)
+				log_cmd_error("Called with -output but the specified object is a cell.\n");
 			log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
 			module->rename(it.second, to_name);
 			return;
@@ -109,6 +114,13 @@ struct RenamePass : public Pass {
 		log("by this command.\n");
 		log("\n");
 		log("\n");
+		log("\n");
+		log("    rename -output old_name new_name\n");
+		log("\n");
+		log("Like above, but also make the wire an output. This will fail if the object is\n");
+		log("not a wire.\n");
+		log("\n");
+		log("\n");
 		log("    rename -src [selection]\n");
 		log("\n");
 		log("Assign names auto-generated from the src attribute to all selected wires and\n");
@@ -148,6 +160,7 @@ struct RenamePass : public Pass {
 		bool flag_enumerate = false;
 		bool flag_hide = false;
 		bool flag_top = false;
+		bool flag_output = false;
 		bool got_mode = false;
 
 		size_t argidx;
@@ -159,6 +172,11 @@ struct RenamePass : public Pass {
 				got_mode = true;
 				continue;
 			}
+			if (arg == "-output" && !got_mode) {
+				flag_output = true;
+				got_mode = true;
+				continue;
+			}
 			if (arg == "-wire" && !got_mode) {
 				flag_wire = true;
 				got_mode = true;
@@ -328,10 +346,12 @@ struct RenamePass : public Pass {
 			if (!design->selected_active_module.empty())
 			{
 				if (design->modules_.count(design->selected_active_module) > 0)
-					rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name);
+					rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name, flag_output);
 			}
 			else
 			{
+				if (flag_output)
+					log_cmd_error("Mode -output requires that there is an active module selected.\n");
 				for (auto &mod : design->modules_) {
 					if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) {
 						to_name = RTLIL::escape_id(to_name);