mirror of https://github.com/YosysHQ/yosys.git
write_aiger() to perform CI/CO post-processing and fix symbols
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7523c87780
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2c1655ae94
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@ -216,12 +216,10 @@ struct XAigerWriter
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SigBit I = sigmap(b);
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if (!w->port_input)
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co_bits.insert(I);
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unused_bits.erase(I);
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}
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else if (cell->output(c.first)) {
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SigBit O = sigmap(b);
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ci_bits.insert(O);
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undriven_bits.erase(O);
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}
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else log_abort();
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if (!type_map.count(cell->type))
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@ -230,6 +228,19 @@ struct XAigerWriter
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//log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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// Do some CI/CO post-processing:
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// Erase all COs that are undriven
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for (auto bit : undriven_bits)
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co_bits.erase(bit);
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// Erase all CIs that are also COs or POs
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for (auto bit : co_bits)
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ci_bits.erase(bit);
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for (auto bit : output_bits)
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ci_bits.erase(bit);
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// CIs cannot be undriven
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for (auto bit : ci_bits)
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undriven_bits.erase(bit);
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for (auto bit : unused_bits)
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undriven_bits.erase(bit);
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@ -255,7 +266,6 @@ struct XAigerWriter
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for (auto bit : ci_bits) {
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aig_m++, aig_i++;
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aig_map[bit] = 2*aig_m;
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co_bits.erase(bit);
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}
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for (auto bit : input_bits) {
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@ -429,8 +439,8 @@ struct XAigerWriter
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for (auto wire : module->wires())
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{
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if (wire->name[0] == '$')
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continue;
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//if (wire->name[0] == '$')
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// continue;
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SigSpec sig = sigmap(wire);
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@ -443,7 +453,7 @@ struct XAigerWriter
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continue;
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}
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if (wire->port_input) {
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if (input_bits.count(sig[i]) || ci_bits.count(SigSpec(sig[i]))) {
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int a = aig_map.at(sig[i]);
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log_assert((a & 1) == 0);
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if (GetSize(wire) != 1)
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@ -452,7 +462,7 @@ struct XAigerWriter
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symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
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}
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if (wire->port_output) {
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if (output_bits.count(SigSpec(wire, i)) || co_bits.count(SigSpec(wire, i))) {
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int o = ordered_outputs.at(SigSpec(wire, i));
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if (GetSize(wire) != 1)
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symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
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