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functional backend: add test to verify test_generic

This commit is contained in:
Emily Schmidt 2024-08-29 13:14:18 +01:00
parent 4eeb8d326a
commit 2b8db94aa0
2 changed files with 10 additions and 3 deletions
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5
Makefile
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@ -1052,9 +1052,10 @@ clean_coverage:
find . -name "*.gcda" -type f -delete
coverage_functional:
rm -rf coverage.info coverage_html
rm -rf coverage.info coverage2.info coverage_html
lcov --capture -d backends/functional --no-external -o coverage.info
genhtml coverage.info --output-directory coverage_html
lcov --capture -d kernel --include kernel/functional.cc --include kernel/functional.h --include kernel/sexpr.cc --include kernel/sexpr.h --include kernel/compute_graph.h --no-external -o coverage2.info
genhtml coverage.info coverage2.info --output-directory coverage_html
qtcreator:
echo "$(CXXFLAGS)" | grep -o '\-D[^ ]*' | tr ' ' '\n' | sed 's/-D/#define /' | sed 's/=/ /'> qtcreator.config

8
tests/functional/test_functional.py
View File

@ -70,4 +70,10 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_smt2 {quote(smt_file)}")
run(['z3', smt_file]) # check if output is valid smtlib before continuing
smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt"))
yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
def test_print_graph(tmp_path):
tb_file = base_path / 'tests/functional/picorv32_tb.v'
cpu_file = base_path / 'tests/functional/picorv32.v'
# currently we only check that we can print the graph without getting an error, not that it prints anything sensibl
yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; clk2fflogic; test_generic")