mirror of https://github.com/YosysHQ/yosys.git
Fix issue #639
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8fde05dfa5
commit
2b89074240
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@ -40,6 +40,8 @@ struct EquivMakeWorker
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pool<SigBit> undriven_bits;
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SigMap assign_map;
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dict<SigBit, pool<Cell*>> bit2driven; // map: bit <--> and its driven cells
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void read_blacklists()
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{
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for (auto fn : blacklists)
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@ -278,12 +280,20 @@ struct EquivMakeWorker
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}
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}
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init_bit2driven();
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pool<Cell*> visited_cells;
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for (auto c : cells_list)
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for (auto &conn : c->connections())
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if (!ct.cell_output(c->type, conn.first)) {
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SigSpec old_sig = assign_map(conn.second);
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SigSpec new_sig = rd_signal_map(old_sig);
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visited_cells.clear();
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if (old_sig != new_sig) {
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if (check_signal_in_fanout(visited_cells, old_sig, new_sig))
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continue;
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log("Changing input %s of cell %s (%s): %s -> %s\n",
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log_id(conn.first), log_id(c), log_id(c->type),
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log_signal(old_sig), log_signal(new_sig));
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@ -378,6 +388,54 @@ struct EquivMakeWorker
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}
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}
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void init_bit2driven()
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{
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for (auto cell : equiv_mod->cells()) {
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if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_"))
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continue;
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for (auto &conn : cell->connections())
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{
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if (yosys_celltypes.cell_input(cell->type, conn.first))
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for (auto bit : assign_map(conn.second))
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{
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bit2driven[bit].insert(cell);
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}
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}
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}
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}
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bool check_signal_in_fanout(pool<Cell*> visited_cells, SigBit source_bit, SigBit target_bit)
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{
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if (source_bit == target_bit)
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return true;
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if (bit2driven.count(source_bit) == 0)
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return false;
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auto driven_cells = bit2driven.at(source_bit);
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for (auto driven_cell: driven_cells)
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{
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if (visited_cells.count(driven_cell) > 0)
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continue;
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visited_cells.insert(driven_cell);
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for (auto &conn: driven_cell->connections())
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{
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if (yosys_celltypes.cell_input(driven_cell->type, conn.first))
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continue;
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for (auto bit: conn.second) {
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bool is_in_fanout = check_signal_in_fanout(visited_cells, bit, target_bit);
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if (is_in_fanout == true)
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return true;
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}
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}
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}
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return false;
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}
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void run()
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{
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copy_to_equiv();
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