riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Stop topological sort at abc_flop_q

This commit is contained in:
Eddie Hung 2019-04-17 12:28:19 -07:00
parent 58847df1b9
commit 2b860809e9
1 changed files with 13 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
backends/aiger/xaiger.cc
View File

@ -180,14 +180,20 @@ struct XAigerWriter
toposort.node(cell->name); toposort.node(cell->name);
for (const auto &conn : cell->connections()) for (const auto &conn : cell->connections())
{ {
// HACK!!! if (!cell->type.in("$_NOT_", "$_AND_")) {
if (cell->type.in("\\SB_DFF", "\\SB_DFFE", "\\SB_DFFESR", "\\SB_DFFSR", "\\SB_DFFESS") && conn.first.in("\\Q")) if (yosys_celltypes.cell_known(cell->type)) {
continue; if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
continue;
if (cell->type == "$memrd" && conn.first == "\\DATA")
continue;
}
if (yosys_celltypes.cell_known(cell->type)) { RTLIL::Module* inst_module = module->design->module(cell->type);
if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA")) log_assert(inst_module);
continue; RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
if (cell->type == "$memrd" && conn.first == "\\DATA") log_assert(inst_module_port);
if (inst_module_port->attributes.count("\\abc_flop_q"))
continue; continue;
} }