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Stop topological sort at abc_flop_q

This commit is contained in:
Eddie Hung 2019-04-17 12:28:19 -07:00
parent 58847df1b9
commit 2b860809e9
1 changed files with 13 additions and 7 deletions
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14
backends/aiger/xaiger.cc
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@ -180,10 +180,7 @@ struct XAigerWriter
toposort.node(cell->name); toposort.node(cell->name);
for (const auto &conn : cell->connections()) for (const auto &conn : cell->connections())
{ {
// HACK!!! if (!cell->type.in("$_NOT_", "$_AND_")) {
if (cell->type.in("\\SB_DFF", "\\SB_DFFE", "\\SB_DFFESR", "\\SB_DFFSR", "\\SB_DFFESS") && conn.first.in("\\Q"))
continue;
if (yosys_celltypes.cell_known(cell->type)) { if (yosys_celltypes.cell_known(cell->type)) {
if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA")) if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
continue; continue;
@ -191,6 +188,15 @@ struct XAigerWriter
continue; continue;
} }
RTLIL::Module* inst_module = module->design->module(cell->type);
log_assert(inst_module);
RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
log_assert(inst_module_port);
if (inst_module_port->attributes.count("\\abc_flop_q"))
continue;
}
if (cell->input(conn.first)) if (cell->input(conn.first))
for (auto bit : sigmap(conn.second)) for (auto bit : sigmap(conn.second))
bit_users[bit].insert(cell->name); bit_users[bit].insert(cell->name);