mirror of https://github.com/YosysHQ/yosys.git
bugpoint: try to remove whole processes first.
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@ -77,6 +77,10 @@ struct BugpointPass : public Pass {
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log(" -connections\n");
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log(" -connections\n");
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log(" try to reconnect ports to 'x.\n");
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log(" try to reconnect ports to 'x.\n");
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log("\n");
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log("\n");
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log(" -processes\n");
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log(" try to remove processes. processes with a (* bugpoint_keep *) attribute\n");
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log(" will be skipped.\n");
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log("\n");
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log(" -assigns\n");
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log(" -assigns\n");
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log(" try to remove process assigns from cases.\n");
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log(" try to remove process assigns from cases.\n");
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log("\n");
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log("\n");
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@ -132,7 +136,7 @@ struct BugpointPass : public Pass {
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return design_copy;
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return design_copy;
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}
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}
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RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections, bool assigns, bool updates)
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RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections, bool processes, bool assigns, bool updates)
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{
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{
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RTLIL::Design *design_copy = new RTLIL::Design;
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RTLIL::Design *design_copy = new RTLIL::Design;
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for (auto module : design->modules())
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for (auto module : design->modules())
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@ -197,7 +201,6 @@ struct BugpointPass : public Pass {
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if (mod->get_blackbox_attribute())
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if (mod->get_blackbox_attribute())
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continue;
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continue;
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Cell *removed_cell = nullptr;
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Cell *removed_cell = nullptr;
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for (auto cell : mod->cells())
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for (auto cell : mod->cells())
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{
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{
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@ -260,6 +263,33 @@ struct BugpointPass : public Pass {
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}
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}
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}
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}
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}
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}
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if (processes)
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{
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for (auto mod : design_copy->modules())
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{
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if (mod->get_blackbox_attribute())
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continue;
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RTLIL::IdString removed_process;
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for (auto process : mod->processes)
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{
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if (process.second->get_bool_attribute(ID::bugpoint_keep))
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continue;
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if (index++ == seed)
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{
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log_header(design, "Trying to remove process %s.%s.\n", log_id(mod), log_id(process.first));
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removed_process = process.first;
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break;
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}
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}
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if (!removed_process.empty()) {
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delete mod->processes[removed_process];
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mod->processes.erase(removed_process);
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return design_copy;
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}
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}
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}
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if (assigns)
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if (assigns)
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{
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{
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for (auto mod : design_copy->modules())
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for (auto mod : design_copy->modules())
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@ -320,7 +350,7 @@ struct BugpointPass : public Pass {
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{
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{
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string yosys_cmd = "yosys", yosys_arg, grep;
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string yosys_cmd = "yosys", yosys_arg, grep;
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bool fast = false, clean = false;
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bool fast = false, clean = false;
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bool modules = false, ports = false, cells = false, connections = false, assigns = false, updates = false, has_part = false;
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bool modules = false, ports = false, cells = false, connections = false, processes = false, assigns = false, updates = false, has_part = false;
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log_header(design, "Executing BUGPOINT pass (minimize testcases).\n");
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log_header(design, "Executing BUGPOINT pass (minimize testcases).\n");
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log_push();
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log_push();
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@ -376,6 +406,11 @@ struct BugpointPass : public Pass {
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has_part = true;
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has_part = true;
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continue;
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continue;
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}
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}
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if (args[argidx] == "-processes") {
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processes = true;
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has_part = true;
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continue;
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}
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if (args[argidx] == "-assigns") {
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if (args[argidx] == "-assigns") {
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assigns = true;
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assigns = true;
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has_part = true;
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has_part = true;
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@ -399,6 +434,7 @@ struct BugpointPass : public Pass {
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ports = true;
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ports = true;
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cells = true;
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cells = true;
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connections = true;
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connections = true;
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processes = true;
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assigns = true;
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assigns = true;
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updates = true;
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updates = true;
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}
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}
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@ -416,7 +452,7 @@ struct BugpointPass : public Pass {
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bool found_something = false, stage2 = false;
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bool found_something = false, stage2 = false;
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while (true)
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while (true)
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{
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{
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if (RTLIL::Design *simplified = simplify_something(crashing_design, seed, stage2, modules, ports, cells, connections, assigns, updates))
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if (RTLIL::Design *simplified = simplify_something(crashing_design, seed, stage2, modules, ports, cells, connections, processes, assigns, updates))
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{
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{
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simplified = clean_design(simplified, fast, /*do_delete=*/true);
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simplified = clean_design(simplified, fast, /*do_delete=*/true);
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