fabulous: Add support for mapping carry chains

Signed-off-by: gatecat <gatecat@ds0.me>

techlibs/fabulous/Makefile.inc

@@ -8,3 +8,4 @@ $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ff_map.v))
 $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ram_regfile.txt))
 $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/regfile_map.v))
 $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/io_map.v))
+$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/arith_map.v))

techlibs/fabulous/arith_map.v

@@ -0,0 +1,65 @@
+`default_nettype none
+
+`ifdef ARITH_ha
+(* techmap_celltype = "$alu" *)
+module _80_fabulous_ha_alu (A, B, CI, BI, X, Y, CO);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+parameter _TECHMAP_CONSTMSK_CI_ = 0;
+parameter _TECHMAP_CONSTVAL_CI_ = 0;
+
+(* force_downto *)
+input [A_WIDTH-1:0] A;
+(* force_downto *)
+input [B_WIDTH-1:0] B;
+input CI, BI;
+(* force_downto *)
+output [Y_WIDTH-1:0] X, Y, CO;
+
+(* force_downto *)
+wire [Y_WIDTH-1:0] A_buf, B_buf;
+\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+(* force_downto *)
+wire [Y_WIDTH-1:0] AA = A_buf;
+(* force_downto *)
+wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+wire [Y_WIDTH:0] CARRY;
+
+
+LUT4_HA #(
+	.INIT(16'b0),
+	.I0MUX(1'b1)
+) carry_statrt (
+	.I0(), .I1(CI), .I2(CI), .I3(),
+	.Ci(),
+	.Co(CARRY[0])
+);
+
+// Carry chain
+genvar i;
+generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+	LUT4_HA #(
+		.INIT(16'b1001_0110_1001_0110), // full adder sum over (I2, I1, I0)
+		.I0MUX(1'b1)
+	) lut_i (
+		.I0(), .I1(AA[i]), .I2(BB[i]), .I3(),
+		.Ci(CARRY[i]),
+		.O(Y[i]),
+		.Co(CARRY[i+1])
+	);
+
+	assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
+end endgenerate
+
+assign X = AA ^ BB;
+
+endmodule
+`endif
+

techlibs/fabulous/prims.v

@@ -24,6 +24,20 @@ module LUT4(output O, input I0, I1, I2, I3);
   assign O = I0 ? s1[1] : s1[0];
 endmodule
 
+module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci);
+  parameter [15:0] INIT = 0;
+  parameter I0MUX = 1'b1;
+
+  wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
+  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
+  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+
+  wire I0_sel = I0MUX ? Ci : I0;
+  assign O = I0_sel ? s1[1] : s1[0];
+
+  assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2);
+endmodule
+
 module LUTFF(input CLK, D, output reg O);
   initial O = 1'b0;
   always @ (posedge CLK) begin

techlibs/fabulous/synth_fabulous.cc

@@ -83,6 +83,9 @@ struct SynthPass : public ScriptPass
 		log("        do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
 		log("        their direct form ($add, $sub, etc.).\n");
 		log("\n");
+		log("    -carry <none|ha>\n");
+		log("        carry mapping style (none, half-adders, ...) default=none\n");
+		log("\n");
 		log("    -noregfile\n");
 		log("        do not map register files\n");
 		log("\n");
@@ -119,7 +122,7 @@ struct SynthPass : public ScriptPass
 		log("\n");
 	}
 
-	string top_module, json_file, blif_file, plib, fsm_opts, memory_opts;
+	string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode;
 	std::vector<string> extra_plib, extra_map;
 
 	bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten;
@@ -137,6 +140,7 @@ struct SynthPass : public ScriptPass
 		noshare = false;
 		iopad = false;
 		complexdff = false;
+		carry_mode = "none";
 		flatten = true;
 		json_file = "";
 		blif_file = "";
@@ -229,6 +233,12 @@ struct SynthPass : public ScriptPass
 				complexdff = true;
 				continue;
 			}
+			if (args[argidx] == "-carry") {
+				carry_mode = args[++argidx];
+				if (carry_mode != "none" && carry_mode != "ha")
+					log_cmd_error("Unsupported carry style: %s\n", carry_mode.c_str());
+				continue;
+			}
 			if (args[argidx] == "-noflatten") {
 				flatten = false;
 				continue;
@@ -326,7 +336,8 @@ struct SynthPass : public ScriptPass
 
 		if (check_label("map_gates")) {
 			run("opt -full");
-			run("techmap -map +/techmap.v");
+			run(stringf("techmap -map +/techmap.v -map +/fabulous/arith_map.v -D ARITH_%s",
+				help_mode ? "<carry>" : carry_mode.c_str()));
 			run("opt -fast");
 		}
 

tests/arch/fabulous/carry.ys

@@ -0,0 +1,9 @@
+read_verilog ../common/add_sub.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/fabulous/prims.v synth_fabulous -carry ha # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-max 10 t:LUT4_HA
+select -assert-max 4 t:LUT1
+select -assert-none t:LUT1 t:LUT4_HA %% t:* %D