mirror of https://github.com/YosysHQ/yosys.git
Bugfix in write_verilog for RTLIL processes
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dac807fb33
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@ -19,11 +19,6 @@
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*
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*
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* A simple and straightforward Verilog backend.
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* A simple and straightforward Verilog backend.
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*
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*
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* Note that RTLIL processes can't always be mapped easily to a Verilog
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* process. Therefore this frontend should only be used to export a
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* Verilog netlist (i.e. after the "proc" pass has converted all processes
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* to logic networks and registers).
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*
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*/
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*/
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#include "kernel/register.h"
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#include "kernel/register.h"
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@ -1135,11 +1130,15 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
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dump_sigspec(f, sw->signal);
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dump_sigspec(f, sw->signal);
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f << stringf(")\n");
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f << stringf(")\n");
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bool got_default = false;
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for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
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for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
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f << stringf("%s ", indent.c_str());
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if ((*it)->compare.size() == 0) {
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if ((*it)->compare.size() == 0)
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if (got_default)
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f << stringf("default");
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continue;
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else {
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f << stringf("%s default", indent.c_str());
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got_default = true;
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} else {
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f << stringf("%s ", indent.c_str());
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for (size_t i = 0; i < (*it)->compare.size(); i++) {
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for (size_t i = 0; i < (*it)->compare.size(); i++) {
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if (i > 0)
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if (i > 0)
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f << stringf(", ");
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f << stringf(", ");
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@ -1244,6 +1243,12 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
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reset_auto_counter(module);
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reset_auto_counter(module);
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active_module = module;
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active_module = module;
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if (!module->processes.empty())
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log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n"
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"can't always be mapped directly to Verilog always blocks. Unintended\n"
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"changes in simulation behavior are possible! Use \"proc\" to convert\n"
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"processes to logic networks and registers.", log_id(module));
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f << stringf("\n");
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f << stringf("\n");
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for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
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for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
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dump_process(f, indent + " ", it->second, true);
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dump_process(f, indent + " ", it->second, true);
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@ -1349,6 +1354,12 @@ struct VerilogBackend : public Backend {
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log(" only write selected modules. modules must be selected entirely or\n");
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log(" only write selected modules. modules must be selected entirely or\n");
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log(" not at all.\n");
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log(" not at all.\n");
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log("\n");
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log("\n");
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log("Note that RTLIL processes can't always be mapped directly to Verilog\n");
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log("always blocks. This frontend should only be used to export an RTLIL\n");
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log("netlist, i.e. after the \"proc\" pass has been used to convert all\n");
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log("processes to logic networks and registers. A warning is generated when\n");
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log("this command is called on a design with RTLIL processes.\n");
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log("\n");
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}
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}
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virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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{
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