From 86ce441af63b639fc4455cdb541048add253de49 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 1 Apr 2022 17:44:00 +0200 Subject: [PATCH] Set init values for wrapped async control signals --- passes/sat/clk2fflogic.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index f37e07a89..bc18bbbd6 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -44,6 +44,7 @@ struct Clk2fflogicPass : public Pass { } SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity, IdString past_sig_id) { Wire *past_sig = module->addWire(past_sig_id, GetSize(sig)); + past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig)); module->addFf(NEW_ID, sig, past_sig); if (polarity) sig = module->Or(NEW_ID, sig, past_sig); @@ -56,6 +57,7 @@ struct Clk2fflogicPass : public Pass { } SigSpec wrap_async_control_gate(Module *module, SigSpec sig, bool polarity) { Wire *past_sig = module->addWire(NEW_ID); + past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig)); module->addFfGate(NEW_ID, sig, past_sig); if (polarity) sig = module->OrGate(NEW_ID, sig, past_sig);