mirror of https://github.com/YosysHQ/yosys.git
xprop: Test fixes and abort on test failure
Use `$finish(0)` to silently exit even when using recent iverlog versions. Run `write_verilog -noexpr` before `write_verilog` as the latter can modify the design. This also enables checking the tests results, as xprop should be in a state where the existing tests pass.
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@ -33,7 +33,7 @@ def add_test(name, src, seq=False):
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print(
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print(
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f"\t@cd {workdir} && python3 -u ../test.py -S {args.seed} -c {args.count}{seq_arg} > test.log 2>&1 || echo {workdir}: failed > status\n"
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f"\t@cd {workdir} && python3 -u ../test.py -S {args.seed} -c {args.count}{seq_arg} > test.log 2>&1 || echo {workdir}: failed > status\n"
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f"\t@cat {workdir}/status\n"
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f"\t@cat {workdir}/status\n"
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# f"\t@grep '^.*: ok' {workdir}/status\n"
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f"\t@grep '^.*: ok' {workdir}/status\n"
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,
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,
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file=makefile,
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file=makefile,
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)
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)
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@ -275,7 +275,7 @@ if "prepare" in steps:
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file=tb_file,
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file=tb_file,
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)
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)
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print(" $finish;", file=tb_file)
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print(" $finish(0);", file=tb_file)
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print("end", file=tb_file)
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print("end", file=tb_file)
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print("endmodule", file=tb_file)
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print("endmodule", file=tb_file)
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@ -344,8 +344,8 @@ for mode in ["", "_xprop"]:
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read_rtlil wrapped{mode}.il
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read_rtlil wrapped{mode}.il
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chformal -remove
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chformal -remove
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dffunmap
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dffunmap
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write_verilog -noparallelcase vsim_expr{mode}.v
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write_verilog -noexpr vsim_noexpr{mode}.v
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write_verilog -noexpr vsim_noexpr{mode}.v
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write_verilog -noparallelcase vsim_expr{mode}.v
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"""
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"""
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)
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)
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