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Improve "mutate" wire coverage metric 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-03-14 23:01:01 +01:00
parent 1b4fdbb0d8
commit 2a4263a75d
1 changed files with 16 additions and 1 deletions
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17
passes/sat/mutate.cc
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@ -289,6 +289,21 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
continue; continue;
SigMap sigmap(module); SigMap sigmap(module);
dict<SigBit, int> bit_user_cnt;
for (auto wire : module->wires()) {
if (wire->name[0] == '\\' && wire->attributes.count("\\src"))
sigmap.add(wire);
}
for (auto cell : module->cells()) {
for (auto &conn : cell->connections()) {
if (cell->output(conn.first))
continue;
for (auto bit : sigmap(conn.second))
bit_user_cnt[bit]++;
}
}
for (auto wire : module->selected_wires()) for (auto wire : module->selected_wires())
{ {
@ -331,7 +346,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
entry.src.insert(s); entry.src.insert(s);
SigBit bit = sigmap(conn.second[i]); SigBit bit = sigmap(conn.second[i]);
if (bit.wire && bit.wire->name[0] == '\\') { if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
for (auto &s : bit.wire->get_strpool_attribute("\\src")) for (auto &s : bit.wire->get_strpool_attribute("\\src"))
entry.src.insert(s); entry.src.insert(s);
entry.wire = bit.wire->name; entry.wire = bit.wire->name;