gatemate: Use `memory_libmap` pass.

This commit is contained in:
Marcelina Kościelnicka 2022-03-06 06:49:18 +01:00
parent 2dcb0797f0
commit 2a2dc12eb6
3 changed files with 931 additions and 785 deletions

View File

@ -1,280 +1,76 @@
bram $__CC_BRAM_CASCADE ram block $__CC_BRAM_TDP_ {
init 1 option "MODE" "20K" {
abits 16 @a16d1 abits 14;
dbits 1 @a16d1 widths 1 2 5 10 20 per_port;
groups 2 cost 129;
ports 1 1 }
wrmode 1 0 option "MODE" "40K" {
enable 1 1 @a16d1 abits 15;
transp 0 0 widths 1 2 5 10 20 40 per_port;
clocks 2 3 cost 257;
clkpol 2 3 }
endbram option "MODE" "CASCADE" {
abits 16;
# hack to enforce same INIT layout as in the other modes
widths 1 2 5 per_port;
cost 513;
}
byte 1;
init no_undef;
port srsw "A" "B" {
clock anyedge;
clken;
option "MODE" "20K" {
width mix;
}
option "MODE" "40K" {
width mix;
}
option "MODE" "CASCADE" {
width mix 1;
}
portoption "WR_MODE" "NO_CHANGE" {
rdwr no_change;
}
portoption "WR_MODE" "WRITE_THROUGH" {
rdwr new;
}
wrbe_separate;
}
}
bram $__CC_BRAM_40K_SDP ram block $__CC_BRAM_SDP_ {
init 1 option "MODE" "20K" {
abits 9 @a9d80 abits 14;
dbits 80 @a9d80 widths 1 2 5 10 20 40 per_port;
groups 2 cost 129;
ports 1 1 }
wrmode 1 0 option "MODE" "40K" {
enable 80 1 @a9d80 abits 15;
transp 0 0 widths 1 2 5 10 20 40 80 per_port;
clocks 2 3 cost 257;
clkpol 2 3 }
endbram byte 1;
init no_undef;
bram $__CC_BRAM_20K_SDP port sr "R" {
init 1 option "MODE" "20K" {
abits 9 @a9d40 width 40;
dbits 40 @a9d40 }
groups 2 option "MODE" "40K" {
ports 1 1 width 80;
wrmode 1 0 }
enable 40 1 @a9d40 clock anyedge;
transp 0 0 clken;
clocks 2 3 }
clkpol 2 3 port sw "W" {
endbram option "MODE" "20K" {
width 40;
bram $__CC_BRAM_40K_TDP }
init 1 option "MODE" "40K" {
abits 10 @a10d40 width 80;
dbits 40 @a10d40 }
abits 11 @a11d20 clock anyedge;
dbits 20 @a11d20 clken;
abits 12 @a12d10 wrbe_separate;
dbits 10 @a12d10 }
abits 13 @a13d5 }
dbits 5 @a13d5
abits 14 @a14d2
dbits 2 @a14d2
abits 15 @a15d1
dbits 1 @a15d1
groups 2
ports 1 1
wrmode 1 0
enable 40 1 @a10d40
enable 20 1 @a11d20
enable 10 1 @a12d10
enable 5 1 @a13d5
enable 2 1 @a14d2
enable 1 1 @a15d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__CC_BRAM_20K_TDP
init 1
abits 10 @a10d20
dbits 20 @a10d20
abits 11 @a11d10
dbits 10 @a11d10
abits 12 @a12d5
dbits 5 @a12d5
abits 13 @a13d2
dbits 2 @a13d2
abits 14 @a14d1
dbits 1 @a14d1
groups 2
ports 1 1
wrmode 1 0
enable 20 1 @a10d20
enable 10 1 @a11d10
enable 5 1 @a12d5
enable 2 1 @a13d2
enable 1 1 @a14d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
match $__CC_BRAM_CASCADE
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 512
min efficiency 5
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_CASCADE
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_CASCADE
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_SDP
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 512
min efficiency 5
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_SDP
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_SDP
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_SDP
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 512
min efficiency 5
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_SDP
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_SDP
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_TDP
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 512
min efficiency 5
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_TDP
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_40K_TDP
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_TDP
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 512
min efficiency 5
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_TDP
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__CC_BRAM_20K_TDP
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
make_transp
endmatch

File diff suppressed because it is too large Load Diff

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@ -237,12 +237,7 @@ struct SynthGateMatePass : public ScriptPass
if (check_label("map_bram", "(skip if '-nobram')") && !nobram) if (check_label("map_bram", "(skip if '-nobram')") && !nobram)
{ {
run("memory_bram -rules +/gatemate/brams.txt"); run("memory_libmap -lib +/gatemate/brams.txt");
run("setundef -zero -params "
"t:$__CC_BRAM_CASCADE "
"t:$__CC_BRAM_40K_SDP t:$__CC_BRAM_20K_SDP "
"t:$__CC_BRAM_20K_TDP t:$__CC_BRAM_40K_TDP "
);
run("techmap -map +/gatemate/brams_map.v"); run("techmap -map +/gatemate/brams_map.v");
} }