mirror of https://github.com/YosysHQ/yosys.git
gatemate: Use `memory_libmap` pass.
This commit is contained in:
Marcelina Kościelnicka
parent
2dcb0797f0
commit
2a2dc12eb6
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@ -1,280 +1,76 @@
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bram $__CC_BRAM_CASCADE
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init 1
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abits 16 @a16d1
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dbits 1 @a16d1
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groups 2
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ports 1 1
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wrmode 1 0
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enable 1 1 @a16d1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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ram block $__CC_BRAM_TDP_ {
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option "MODE" "20K" {
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abits 14;
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widths 1 2 5 10 20 per_port;
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cost 129;
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}
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option "MODE" "40K" {
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abits 15;
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widths 1 2 5 10 20 40 per_port;
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cost 257;
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}
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option "MODE" "CASCADE" {
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abits 16;
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# hack to enforce same INIT layout as in the other modes
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widths 1 2 5 per_port;
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cost 513;
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}
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byte 1;
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init no_undef;
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port srsw "A" "B" {
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clock anyedge;
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clken;
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option "MODE" "20K" {
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width mix;
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}
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option "MODE" "40K" {
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width mix;
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}
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option "MODE" "CASCADE" {
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width mix 1;
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}
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portoption "WR_MODE" "NO_CHANGE" {
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rdwr no_change;
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}
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portoption "WR_MODE" "WRITE_THROUGH" {
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rdwr new;
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}
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wrbe_separate;
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}
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}
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bram $__CC_BRAM_40K_SDP
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init 1
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abits 9 @a9d80
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dbits 80 @a9d80
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groups 2
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ports 1 1
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wrmode 1 0
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enable 80 1 @a9d80
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__CC_BRAM_20K_SDP
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init 1
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abits 9 @a9d40
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dbits 40 @a9d40
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groups 2
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ports 1 1
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wrmode 1 0
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enable 40 1 @a9d40
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__CC_BRAM_40K_TDP
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init 1
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abits 10 @a10d40
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dbits 40 @a10d40
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abits 11 @a11d20
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dbits 20 @a11d20
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abits 12 @a12d10
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dbits 10 @a12d10
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abits 13 @a13d5
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dbits 5 @a13d5
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abits 14 @a14d2
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dbits 2 @a14d2
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abits 15 @a15d1
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dbits 1 @a15d1
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groups 2
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ports 1 1
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wrmode 1 0
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enable 40 1 @a10d40
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enable 20 1 @a11d20
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enable 10 1 @a12d10
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enable 5 1 @a13d5
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enable 2 1 @a14d2
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enable 1 1 @a15d1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__CC_BRAM_20K_TDP
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init 1
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abits 10 @a10d20
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dbits 20 @a10d20
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abits 11 @a11d10
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dbits 10 @a11d10
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abits 12 @a12d5
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dbits 5 @a12d5
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abits 13 @a13d2
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dbits 2 @a13d2
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abits 14 @a14d1
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dbits 1 @a14d1
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groups 2
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ports 1 1
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wrmode 1 0
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enable 20 1 @a10d20
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enable 10 1 @a11d10
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enable 5 1 @a12d5
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enable 2 1 @a13d2
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enable 1 1 @a14d1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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match $__CC_BRAM_CASCADE
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# implicitly requested RAM or ROM
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attribute !syn_ramstyle syn_ramstyle=auto
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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min bits 512
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min efficiency 5
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_CASCADE
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# explicitly requested RAM
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attribute syn_ramstyle=block_ram ram_block
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attribute !syn_romstyle
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attribute !rom_block
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attribute !logic_block
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min wports 1
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_CASCADE
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# explicitly requested ROM
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attribute syn_romstyle=ebr rom_block
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attribute !syn_ramstyle
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attribute !ram_block
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attribute !logic_block
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max wports 0
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_40K_SDP
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# implicitly requested RAM or ROM
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attribute !syn_ramstyle syn_ramstyle=auto
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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min bits 512
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min efficiency 5
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_40K_SDP
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# explicitly requested RAM
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attribute syn_ramstyle=block_ram ram_block
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attribute !syn_romstyle
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attribute !rom_block
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attribute !logic_block
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min wports 1
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_40K_SDP
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# explicitly requested ROM
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attribute syn_romstyle=ebr rom_block
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attribute !syn_ramstyle
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attribute !ram_block
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attribute !logic_block
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max wports 0
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_20K_SDP
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# implicitly requested RAM or ROM
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attribute !syn_ramstyle syn_ramstyle=auto
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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min bits 512
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min efficiency 5
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_20K_SDP
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# explicitly requested RAM
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attribute syn_ramstyle=block_ram ram_block
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attribute !syn_romstyle
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attribute !rom_block
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attribute !logic_block
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min wports 1
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_20K_SDP
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# explicitly requested ROM
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attribute syn_romstyle=ebr rom_block
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attribute !syn_ramstyle
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attribute !ram_block
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attribute !logic_block
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max wports 0
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_40K_TDP
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# implicitly requested RAM or ROM
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attribute !syn_ramstyle syn_ramstyle=auto
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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min bits 512
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min efficiency 5
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_40K_TDP
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# explicitly requested RAM
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attribute syn_ramstyle=block_ram ram_block
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attribute !syn_romstyle
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attribute !rom_block
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attribute !logic_block
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min wports 1
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_40K_TDP
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# explicitly requested ROM
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attribute syn_romstyle=ebr rom_block
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attribute !syn_ramstyle
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attribute !ram_block
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attribute !logic_block
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max wports 0
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_20K_TDP
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# implicitly requested RAM or ROM
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attribute !syn_ramstyle syn_ramstyle=auto
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attribute !syn_romstyle syn_romstyle=auto
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attribute !ram_block
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attribute !rom_block
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attribute !logic_block
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min bits 512
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min efficiency 5
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_20K_TDP
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# explicitly requested RAM
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attribute syn_ramstyle=block_ram ram_block
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attribute !syn_romstyle
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attribute !rom_block
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attribute !logic_block
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min wports 1
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__CC_BRAM_20K_TDP
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# explicitly requested ROM
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attribute syn_romstyle=ebr rom_block
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attribute !syn_ramstyle
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attribute !ram_block
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attribute !logic_block
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max wports 0
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shuffle_enable A
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make_transp
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endmatch
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ram block $__CC_BRAM_SDP_ {
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option "MODE" "20K" {
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abits 14;
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widths 1 2 5 10 20 40 per_port;
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cost 129;
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}
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option "MODE" "40K" {
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abits 15;
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widths 1 2 5 10 20 40 80 per_port;
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cost 257;
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}
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byte 1;
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init no_undef;
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port sr "R" {
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option "MODE" "20K" {
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width 40;
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}
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option "MODE" "40K" {
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width 80;
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}
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clock anyedge;
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clken;
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}
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port sw "W" {
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option "MODE" "20K" {
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width 40;
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}
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option "MODE" "40K" {
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width 80;
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}
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clock anyedge;
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clken;
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wrbe_separate;
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}
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}
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File diff suppressed because it is too large
Load Diff
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@ -237,12 +237,7 @@ struct SynthGateMatePass : public ScriptPass
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if (check_label("map_bram", "(skip if '-nobram')") && !nobram)
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{
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run("memory_bram -rules +/gatemate/brams.txt");
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run("setundef -zero -params "
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"t:$__CC_BRAM_CASCADE "
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"t:$__CC_BRAM_40K_SDP t:$__CC_BRAM_20K_SDP "
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"t:$__CC_BRAM_20K_TDP t:$__CC_BRAM_40K_TDP "
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);
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run("memory_libmap -lib +/gatemate/brams.txt");
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run("techmap -map +/gatemate/brams_map.v");
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}
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