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Add DSP_A_MAXWIDTH_PARTIAL, refactor

This commit is contained in:
Eddie Hung 2019-08-13 10:21:24 -07:00
parent f890cfb63b
commit 2a1b98d478
2 changed files with 111 additions and 145 deletions
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254
techlibs/common/mul2dsp.v
View File

@ -27,20 +27,30 @@
*/ */
`ifndef DSP_A_MAXWIDTH `ifndef DSP_A_MAXWIDTH
$error("Macro DSP_A_MAXWIDTH must be defined"); $fatal(1, "Macro DSP_A_MAXWIDTH must be defined");
`endif `endif
`ifndef DSP_B_MAXWIDTH `ifndef DSP_B_MAXWIDTH
$error("Macro DSP_B_MAXWIDTH must be defined"); $fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
`endif
`ifndef DSP_B_MAXWIDTH
$fatal(1, "Macro DSP_B_MAXWIDTH must be defined");
`endif
`ifndef DSP_A_MAXWIDTH_PARTIAL
`define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH
`endif
`ifndef DSP_B_MAXWIDTH_PARTIAL
`define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH
`endif `endif
`ifndef DSP_NAME `ifndef DSP_NAME
$error("Macro DSP_NAME must be defined"); $fatal(1, "Macro DSP_NAME must be defined");
`endif `endif
`define MAX(a,b) (a > b ? a : b) `define MAX(a,b) (a > b ? a : b)
`define MIN(a,b) (a < b ? a : b) `define MIN(a,b) (a < b ? a : b)
module \$mul (A, B, Y); (* techmap_celltype = "$mul $__mul" *)
module _80_mul (A, B, Y);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
parameter B_SIGNED = 0; parameter B_SIGNED = 0;
parameter A_WIDTH = 1; parameter A_WIDTH = 1;
@ -51,12 +61,26 @@ module \$mul (A, B, Y);
input [B_WIDTH-1:0] B; input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
generate generate
if (A_SIGNED != B_SIGNED) if (0) begin end
`ifdef DSP_A_MINWIDTH
else if (A_WIDTH < `DSP_A_MINWIDTH)
wire _TECHMAP_FAIL_ = 1;
`endif
`ifdef DSP_B_MINWIDTH
else if (B_WIDTH < `DSP_B_MINWIDTH)
wire _TECHMAP_FAIL_ = 1;
`endif
`ifdef DSP_Y_MINWIDTH
else if (Y_WIDTH < `DSP_Y_MINWIDTH)
wire _TECHMAP_FAIL_ = 1;
`endif
else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED)
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
// NB: A_SIGNED == B_SIGNED from here
`ifdef DSP_SIGNEDONLY `ifdef DSP_SIGNEDONLY
else if (!A_SIGNED) else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED)
\$mul #( \$mul #(
.A_SIGNED(1), .A_SIGNED(1),
.B_SIGNED(1), .B_SIGNED(1),
@ -81,102 +105,53 @@ module \$mul (A, B, Y);
.B(A), .B(A),
.Y(Y) .Y(Y)
); );
else else begin
\$__mul #( wire [1023:0] _TECHMAP_DO_ = "proc; clean";
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A),
.B(B),
.Y(Y)
);
endgenerate
endmodule
module \$__mul (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
`ifdef DSP_SIGNEDONLY `ifdef DSP_SIGNEDONLY
localparam sign_headroom = 1; localparam sign_headroom = 1;
`else `else
localparam sign_headroom = 0; localparam sign_headroom = 0;
`endif `endif
genvar i; genvar i;
generate if (A_WIDTH > `DSP_A_MAXWIDTH) begin
if (0) begin end localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
`ifdef DSP_A_MINWIDTH localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);
else if (A_WIDTH < `DSP_A_MINWIDTH) localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
wire _TECHMAP_FAIL_ = 1; localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
`endif
`ifdef DSP_B_MINWIDTH
else if (B_WIDTH < `DSP_B_MINWIDTH)
wire _TECHMAP_FAIL_ = 1;
`endif
`ifdef DSP_Y_MINWIDTH
else if (Y_WIDTH < `DSP_Y_MINWIDTH)
wire _TECHMAP_FAIL_ = 1;
`endif
else if (A_WIDTH > `DSP_A_MAXWIDTH) begin
localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom);
localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH);
localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, B_WIDTH+A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom));
if (A_SIGNED && B_SIGNED) begin if (A_SIGNED && B_SIGNED) begin
wire signed [partial_Y_WIDTH-1:0] partial [n-2:0]; wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
wire signed [last_Y_WIDTH-1:0] last_partial; wire signed [last_Y_WIDTH-1:0] last_partial;
wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; wire signed [Y_WIDTH-1:0] partial_sum [n:0];
end end
else begin else begin
wire [partial_Y_WIDTH-1:0] partial [n-1:0]; wire [partial_Y_WIDTH-1:0] partial [n-1:0];
wire [last_Y_WIDTH-1:0] last_partial; wire [last_Y_WIDTH-1:0] last_partial;
wire [Y_WIDTH-1:0] partial_sum [n-1:0]; wire [Y_WIDTH-1:0] partial_sum [n:0];
end end
\$__mul #( for (i = 0; i < n; i=i+1) begin:slice
.A_SIGNED(sign_headroom),
.B_SIGNED(B_SIGNED),
.A_WIDTH(`DSP_A_MAXWIDTH),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(partial_Y_WIDTH)
) mul_slice_first (
.A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1 : 0]}),
.B(B),
.Y(partial[0])
);
assign partial_sum[0] = partial[0];
for (i = 1; i < n-1; i=i+1) begin:slice
\$__mul #( \$__mul #(
.A_SIGNED(sign_headroom), .A_SIGNED(sign_headroom),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(`DSP_A_MAXWIDTH), .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(partial_Y_WIDTH) .Y_WIDTH(partial_Y_WIDTH)
) mul_slice ( ) mul_slice (
.A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH-sign_headroom) +: `DSP_A_MAXWIDTH-sign_headroom]}), .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),
.B(B), .B(B),
.Y(partial[i]) .Y(partial[i])
); );
// TODO: Currently a 'cascade' approach to summing the partial // TODO: Currently a 'cascade' approach to summing the partial
// products is taken here, but a more efficient 'binary // products is taken here, but a more efficient 'binary
// reduction' approach also exists... // reduction' approach also exists...
assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; if (i == 0)
assign partial_sum[i] = partial[i];
else
assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
end end
localparam last_A_WIDTH = A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom);
\$__mul #( \$__mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
@ -188,56 +163,46 @@ module \$__mul (A, B, Y);
.B(B), .B(B),
.Y(last_partial) .Y(last_partial)
); );
assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
assign Y = partial_sum[n-1]; assign Y = partial_sum[n];
end end
else if (B_WIDTH > `DSP_B_MAXWIDTH) begin else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom); localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);
localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)); localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
if (A_SIGNED && B_SIGNED) begin if (A_SIGNED && B_SIGNED) begin
wire signed [partial_Y_WIDTH-1:0] partial [n-2:0]; wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
wire signed [last_Y_WIDTH-1:0] last_partial; wire signed [last_Y_WIDTH-1:0] last_partial;
wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; wire signed [Y_WIDTH-1:0] partial_sum [n:0];
end end
else begin else begin
wire [partial_Y_WIDTH-1:0] partial [n-1:0]; wire [partial_Y_WIDTH-1:0] partial [n-1:0];
wire [last_Y_WIDTH-1:0] last_partial; wire [last_Y_WIDTH-1:0] last_partial;
wire [Y_WIDTH-1:0] partial_sum [n-1:0]; wire [Y_WIDTH-1:0] partial_sum [n:0];
end end
\$__mul #( for (i = 0; i < n; i=i+1) begin:slice
.A_SIGNED(A_SIGNED),
.B_SIGNED(sign_headroom),
.A_WIDTH(A_WIDTH),
.B_WIDTH(`DSP_B_MAXWIDTH),
.Y_WIDTH(partial_Y_WIDTH)
) mul_first (
.A(A),
.B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1 : 0]}),
.Y(partial[0])
);
assign partial_sum[0] = partial[0];
for (i = 1; i < n-1; i=i+1) begin:slice
\$__mul #( \$__mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(sign_headroom), .B_SIGNED(sign_headroom),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
.B_WIDTH(`DSP_B_MAXWIDTH), .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL),
.Y_WIDTH(partial_Y_WIDTH) .Y_WIDTH(partial_Y_WIDTH)
) mul ( ) mul (
.A(A), .A(A),
.B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),
.Y(partial[i]) .Y(partial[i])
); );
// TODO: Currently a 'cascade' approach to summing the partial // TODO: Currently a 'cascade' approach to summing the partial
// products is taken here, but a more efficient 'binary // products is taken here, but a more efficient 'binary
// reduction' approach also exists... // reduction' approach also exists...
assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; if (i == 0)
assign partial_sum[i] = partial[i];
else
assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
end end
localparam last_B_WIDTH = B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom);
\$__mul #( \$__mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
@ -249,10 +214,10 @@ module \$__mul (A, B, Y);
.B(B[B_WIDTH-1 -: last_B_WIDTH]), .B(B[B_WIDTH-1 -: last_B_WIDTH]),
.Y(last_partial) .Y(last_partial)
); );
assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
assign Y = partial_sum[n-1]; assign Y = partial_sum[n];
end end
else begin else begin
if (A_SIGNED) if (A_SIGNED)
wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A); wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
else else
@ -274,11 +239,12 @@ module \$__mul (A, B, Y);
.Y(Y) .Y(Y)
); );
end end
end
endgenerate endgenerate
endmodule endmodule
(* techmap_celltype = "$__mul" *) (* techmap_celltype = "$mul $__mul" *)
module $__soft_mul (A, B, Y); module _90_soft_mul (A, B, Y);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
parameter B_SIGNED = 0; parameter B_SIGNED = 0;
parameter A_WIDTH = 1; parameter A_WIDTH = 1;
@ -292,41 +258,41 @@ module $__soft_mul (A, B, Y);
// Indirection necessary since mapping // Indirection necessary since mapping
// back to $mul will cause recursion // back to $mul will cause recursion
generate generate
if (A_SIGNED && !B_SIGNED) if (A_SIGNED && !B_SIGNED)
\$__soft__mul #( \$__soft_mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(1), .B_SIGNED(1),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH+1), .B_WIDTH(B_WIDTH+1),
.Y_WIDTH(Y_WIDTH) .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A(A), .A(A),
.B({1'b0,B}), .B({1'b0,B}),
.Y(Y) .Y(Y)
); );
else if (!A_SIGNED && B_SIGNED) else if (!A_SIGNED && B_SIGNED)
\$__soft_mul #( \$__soft_mul #(
.A_SIGNED(1), .A_SIGNED(1),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH+1), .A_WIDTH(A_WIDTH+1),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH) .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A({1'b0,A}), .A({1'b0,A}),
.B(B), .B(B),
.Y(Y) .Y(Y)
); );
else else
\$__soft_mul #( \$__soft_mul #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH) .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A(A), .A(A),
.B(B), .B(B),
.Y(Y) .Y(Y)
); );
endgenerate endgenerate
endmodule endmodule

2
techlibs/xilinx/synth_xilinx.cc
View File

@ -286,7 +286,7 @@ struct SynthXilinxPass : public ScriptPass
if (!nodsp || help_mode) { if (!nodsp || help_mode) {
// NB: Xilinx multipliers are signed only // NB: Xilinx multipliers are signed only
run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')");
run("opt_expr -fine", " (skip if '-nodsp')"); run("opt_expr -fine", " (skip if '-nodsp')");
run("wreduce", " (skip if '-nodsp')"); run("wreduce", " (skip if '-nodsp')");
run("xilinx_dsp", " (skip if '-nodsp')"); run("xilinx_dsp", " (skip if '-nodsp')");