From d5aac2650f9169b2b890854083c5502b84adf115 Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Thu, 18 Oct 2018 21:27:04 +0200 Subject: [PATCH] Basic test for checking correct synthesis of SystemVerilog interfaces --- Makefile | 2 + tests/svinterfaces/run-test.sh | 5 + tests/svinterfaces/runone.sh | 41 +++++++ .../{simple => svinterfaces}/svinterface1.sv | 45 ++++++-- tests/svinterfaces/svinterface1_ref.v | 107 ++++++++++++++++++ tests/svinterfaces/svinterface1_tb.v | 57 ++++++++++ 6 files changed, 248 insertions(+), 9 deletions(-) create mode 100755 tests/svinterfaces/run-test.sh create mode 100755 tests/svinterfaces/runone.sh rename tests/{simple => svinterfaces}/svinterface1.sv (50%) create mode 100644 tests/svinterfaces/svinterface1_ref.v create mode 100644 tests/svinterfaces/svinterface1_tb.v diff --git a/Makefile b/Makefile index a5a4f15ba..090c94648 100644 --- a/Makefile +++ b/Makefile @@ -573,6 +573,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/bram && bash run-test.sh $(SEEDOPT) +cd tests/various && bash run-test.sh +cd tests/sat && bash run-test.sh + +cd tests/svinterfaces && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" @@ -655,6 +656,7 @@ clean: rm -rf tests/sat/*.log tests/techmap/*.log tests/various/*.log rm -rf tests/bram/temp tests/fsm/temp tests/realmath/temp tests/share/temp tests/smv/temp rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_* + rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff rm -f tests/tools/cmp_tbdata clean-abc: diff --git a/tests/svinterfaces/run-test.sh b/tests/svinterfaces/run-test.sh new file mode 100755 index 000000000..1630859bd --- /dev/null +++ b/tests/svinterfaces/run-test.sh @@ -0,0 +1,5 @@ +#/bin/bash -e + + + +./runone.sh svinterface1 diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh new file mode 100755 index 000000000..345801389 --- /dev/null +++ b/tests/svinterfaces/runone.sh @@ -0,0 +1,41 @@ +#!/bin/bash + + +TESTNAME=$1 + +STDOUTFILE=${TESTNAME}.log_stdout +STDERRFILE=${TESTNAME}.log_stderr + +echo "" > $STDOUTFILE +echo "" > $STDERRFILE + +echo -n "Test: ${TESTNAME} -> " + +$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE +$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE + +rm -f a.out reference_result.txt dut_result.txt + +set -e + +iverilog -g2012 ${TESTNAME}_syn.v +iverilog -g2012 ${TESTNAME}_ref_syn.v + +set +e + +iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v +./a.out +mv output.txt reference_result.txt +iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v +./a.out +mv output.txt dut_result.txt + +diff reference_result.txt dut_result.txt > ${TESTNAME}.diff +RET=$? +if [ "$RET" != "0" ] ; then + echo "ERROR!" + exit -1 +fi + +echo "ok" +exit 0 diff --git a/tests/simple/svinterface1.sv b/tests/svinterfaces/svinterface1.sv similarity index 50% rename from tests/simple/svinterface1.sv rename to tests/svinterfaces/svinterface1.sv index 64383a06c..6d60b4880 100644 --- a/tests/simple/svinterface1.sv +++ b/tests/svinterfaces/svinterface1.sv @@ -3,8 +3,11 @@ module TopModule( input logic clk, input logic rst, + output logic [21:0] outOther, input logic [1:0] sig, - output logic [1:0] sig_out); + input logic flip, + output logic [1:0] sig_out, + output logic [15:0] passThrough); MyInterface #(.WIDTH(4)) MyInterfaceInstance(); @@ -12,14 +15,16 @@ module TopModule( .clk(clk), .rst(rst), .u_MyInterface(MyInterfaceInstance), + .outOther(outOther), .sig (sig) ); assign sig_out = MyInterfaceInstance.mysig_out; - assign MyInterfaceInstance.setting = 1; -// assign MyInterfaceInstance.other_setting[2:0] = 3'b101; + assign MyInterfaceInstance.setting = flip; + + assign passThrough = MyInterfaceInstance.passThrough; endmodule @@ -32,16 +37,20 @@ interface MyInterface #( logic [1:0] mysig_out; + logic [15:0] passThrough; + modport submodule1 ( input setting, output other_setting, - output mysig_out + output mysig_out, + output passThrough ); modport submodule2 ( input setting, output other_setting, - input mysig_out + input mysig_out, + output passThrough ); endinterface @@ -51,7 +60,8 @@ module SubModule1( input logic clk, input logic rst, MyInterface.submodule1 u_MyInterface, - input logic [1:0] sig + input logic [1:0] sig, + output logic [21:0] outOther ); @@ -71,9 +81,14 @@ module SubModule1( .clk(clk), .rst(rst), .u_MyInterfaceInSub2(u_MyInterface), - .sig (sig) + .u_MyInterfaceInSub3(MyInterfaceInstanceInSub) ); + assign outOther = MyInterfaceInstanceInSub.other_setting; + + assign MyInterfaceInstanceInSub.setting = 0; + assign MyInterfaceInstanceInSub.mysig_out = sig; + endmodule module SubModule2( @@ -81,10 +96,22 @@ module SubModule2( input logic clk, input logic rst, MyInterface.submodule2 u_MyInterfaceInSub2, - input logic [1:0] sig + MyInterface.submodule2 u_MyInterfaceInSub3 ); - assign u_MyInterfaceInSub2.other_setting[2:0] = 9; + always_comb begin + if (u_MyInterfaceInSub3.mysig_out == 2'b00) + u_MyInterfaceInSub3.other_setting[21:0] = 1000; + else if (u_MyInterfaceInSub3.mysig_out == 2'b01) + u_MyInterfaceInSub3.other_setting[21:0] = 2000; + else if (u_MyInterfaceInSub3.mysig_out == 2'b10) + u_MyInterfaceInSub3.other_setting[21:0] = 3000; + else + u_MyInterfaceInSub3.other_setting[21:0] = 4000; + end + + assign u_MyInterfaceInSub2.passThrough[7:0] = 124; + assign u_MyInterfaceInSub2.passThrough[15:8] = 200; endmodule diff --git a/tests/svinterfaces/svinterface1_ref.v b/tests/svinterfaces/svinterface1_ref.v new file mode 100644 index 000000000..b119f4037 --- /dev/null +++ b/tests/svinterfaces/svinterface1_ref.v @@ -0,0 +1,107 @@ + +module TopModule( + input logic clk, + input logic rst, + input logic [1:0] sig, + input logic flip, + output logic [15:0] passThrough, + output logic [21:0] outOther, + output logic [1:0] sig_out); + + + logic MyInterfaceInstance_setting; + logic [3:0] MyInterfaceInstance_other_setting; + logic [1:0] MyInterfaceInstance_mysig_out; + + SubModule1 u_SubModule1 ( + .clk(clk), + .rst(rst), + .u_MyInterface_setting(MyInterfaceInstance_setting), + .u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out), + .u_MyInterface_other_setting(MyInterfaceInstance_other_setting), + .outOther(outOther), + .passThrough (passThrough), + .sig (sig) + ); + + assign sig_out = MyInterfaceInstance_mysig_out; + + + assign MyInterfaceInstance_setting = flip; + +endmodule + + +module SubModule1( + input logic clk, + input logic rst, + input logic u_MyInterface_setting, + output logic [3:0] u_MyInterface_other_setting, + output logic [1:0] u_MyInterface_mysig_out, + output logic [21:0] outOther, + input logic [1:0] sig, + output logic [15:0] passThrough + ); + + always @(posedge clk or posedge rst) + if(rst) + u_MyInterface_mysig_out <= 0; + else begin + if(u_MyInterface_setting) + u_MyInterface_mysig_out <= sig; + else + u_MyInterface_mysig_out <= ~sig; + end + + logic MyInterfaceInstanceInSub_setting; + logic [21:0] MyInterfaceInstanceInSub_other_setting; + logic [1:0] MyInterfaceInstanceInSub_mysig_out; + + + SubModule2 u_SubModule2 ( + .clk(clk), + .rst(rst), + .u_MyInterfaceInSub2_setting(u_MyInterface_setting), + .u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out), + .u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting), + .u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting), + .u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out), + .u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting), + .passThrough (passThrough) + ); + assign outOther = MyInterfaceInstanceInSub_other_setting; + + assign MyInterfaceInstanceInSub_setting = 0; + assign MyInterfaceInstanceInSub_mysig_out = sig; + +endmodule + +module SubModule2( + + input logic clk, + input logic rst, + input logic u_MyInterfaceInSub2_setting, + output logic [3:0] u_MyInterfaceInSub2_other_setting, + input logic [1:0] u_MyInterfaceInSub2_mysig_out, + input logic u_MyInterfaceInSub3_setting, + output logic [21:0] u_MyInterfaceInSub3_other_setting, + input logic [1:0] u_MyInterfaceInSub3_mysig_out, + output logic [15:0] passThrough + + ); + + always @(u_MyInterfaceInSub3_mysig_out) begin + if (u_MyInterfaceInSub3_mysig_out == 2'b00) + u_MyInterfaceInSub3_other_setting[21:0] = 1000; + else if (u_MyInterfaceInSub3_mysig_out == 2'b01) + u_MyInterfaceInSub3_other_setting[21:0] = 2000; + else if (u_MyInterfaceInSub3_mysig_out == 2'b10) + u_MyInterfaceInSub3_other_setting[21:0] = 3000; + else + u_MyInterfaceInSub3_other_setting[21:0] = 4000; + end + + assign passThrough[7:0] = 124; + assign passThrough[15:8] = 200; + +endmodule diff --git a/tests/svinterfaces/svinterface1_tb.v b/tests/svinterfaces/svinterface1_tb.v new file mode 100644 index 000000000..44c3b5f68 --- /dev/null +++ b/tests/svinterfaces/svinterface1_tb.v @@ -0,0 +1,57 @@ +`timescale 1ns/10ps + +module svinterface1_tb; + + + logic clk; + logic rst; + logic [21:0] outOther; + logic [1:0] sig; + logic [1:0] sig_out; + logic flip; + logic [15:0] passThrough; + integer outfile; + + TopModule u_dut ( + .clk(clk), + .rst(rst), + .outOther(outOther), + .sig(sig), + .flip(flip), + .passThrough(passThrough), + .sig_out(sig_out) + ); + + initial begin + clk = 0; + while(1) begin + clk = ~clk; + #50; + end + end + + initial begin + outfile = $fopen("output.txt"); + rst = 1; + sig = 0; + flip = 0; + @(posedge clk); + #(2); + rst = 0; + @(posedge clk); + for(int j=0;j<2;j++) begin + for(int i=0;i<20;i++) begin + #(2); + flip = j; + sig = i; + @(posedge clk); + end + end + $finish; + end + + always @(negedge clk) begin + $fdisplay(outfile, "%d %d %d", outOther, sig_out, passThrough); + end + +endmodule