From 60eaaf6e0f7bf1020ee62f8b77e8ead5dcbb8f99 Mon Sep 17 00:00:00 2001
From: acw1251 <acwright@mit.edu>
Date: Wed, 19 Jun 2019 15:39:56 -0400
Subject: [PATCH 001/111] Fixed pyosys commands returning RTLIL::SigSig

---
 misc/py_wrap_generator.py | 26 ++++++++++----------------
 1 file changed, 10 insertions(+), 16 deletions(-)

diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py
index 9e5727499..48a54b643 100644
--- a/misc/py_wrap_generator.py
+++ b/misc/py_wrap_generator.py
@@ -508,23 +508,17 @@ class TupleTranslator(PythonDictTranslator):
 	#Generate c++ code to translate to a boost::python::tuple
 	@classmethod
 	def translate_cpp(c, varname, types, prefix, ref):
-		text  = prefix + TupleTranslator.typename + " " + varname + "___tmp = boost::python::make_tuple(" + varname + ".first, " + varname + ".second);"
-		return text
-		tmp_name = "tmp_" + str(Translator.tmp_cntr)
-		Translator.tmp_cntr = Translator.tmp_cntr + 1
-		if ref:
-			text += prefix + "for(auto " + tmp_name + " : *" + varname + ")"
+		# if the tuple is a pair of SigSpecs (aka SigSig), then we need
+		# to call get_py_obj() on each item in the tuple
+		if types[0].name in classnames:
+			first_var = types[0].name + "::get_py_obj(" + varname + ".first)"
 		else:
-			text += prefix + "for(auto " + tmp_name + " : " + varname + ")"
-		text += prefix + "{"
-		if types[0].name.split(" ")[-1] in primitive_types or types[0].name in enum_names:
-			text += prefix + "\t" + varname + "___tmp.append(" + tmp_name + ");"
-		elif types[0].name in known_containers:
-			text += known_containers[types[0].name].translate_cpp(tmp_name, types[0].cont.args, prefix + "\t", types[1].attr_type == attr_types.star)
-			text += prefix + "\t" + varname + "___tmp.append(" + types[0].name + "::get_py_obj(" + tmp_name + "___tmp);"
-		elif types[0].name in classnames:
-			text += prefix + "\t" + varname + "___tmp.append(" + types[0].name + "::get_py_obj(" + tmp_name + "));"
-		text += prefix + "}"
+			first_var = varname + ".first"
+		if types[1].name in classnames:
+			second_var = types[1].name + "::get_py_obj(" + varname + ".second)"
+		else:
+			second_var = varname + ".second"
+		text  = prefix + TupleTranslator.typename + " " + varname + "___tmp = boost::python::make_tuple(" + first_var + ", " + second_var + ");"
 		return text
 
 #Associate the Translators with their c++ type

From fdf0e82472d978ddbe0a287bdda8b5341b814d3e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 11:16:15 -0700
Subject: [PATCH 002/111] Add missing CHANGELOG entries

---
 CHANGELOG | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/CHANGELOG b/CHANGELOG
index 4d0c31e28..03ab2a7cc 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -23,6 +23,9 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "muxcover -nopartial"
     - Added "muxpack" pass
     - Added "pmux2shiftx -norange"
+    - Added "synth_xilinx -nocarry"
+    - Added "synth_xilinx -nowidelut"
+    - Added "synth_ecp5 -nowidelut"
     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 

From 43069e9eb91bf76164e80d6ea65443bd05567d64 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 2 Jul 2019 10:06:56 -0700
Subject: [PATCH 003/111] Checkout yosys-0.9-rc branch of yosys-tests

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 67bcb3d15..383ec9e55 100644
--- a/Makefile
+++ b/Makefile
@@ -702,7 +702,7 @@ vloghtb: $(TARGETS) $(EXTRA_TARGETS)
 
 ystests: $(TARGETS) $(EXTRA_TARGETS)
 	rm -rf tests/ystests
-	git clone https://github.com/YosysHQ/yosys-tests.git tests/ystests
+	git clone -b yosys-0.9-rc https://github.com/YosysHQ/yosys-tests.git tests/ystests
 	+$(MAKE) PATH="$$PWD:$$PATH" -C tests/ystests
 	@echo ""
 	@echo "  Finished \"make ystests\"."

From ef0823690c386c405fdd0ca2a3f45af8788a19aa Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 28 Jun 2019 10:30:31 +0200
Subject: [PATCH 004/111] Merge pull request #1146 from gsomlo/gls-test-abc-ext

tests: use optional ABCEXTERNAL when specified
---
 Makefile                   | 10 ++++++++--
 tests/aiger/run-test.sh    | 14 ++++++++++++--
 tests/memories/run-test.sh |  6 ++++--
 tests/tools/autotest.sh    |  7 +++++--
 4 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/Makefile b/Makefile
index 383ec9e55..bbae8c159 100644
--- a/Makefile
+++ b/Makefile
@@ -666,6 +666,12 @@ else
 SEEDOPT=""
 endif
 
+ifneq ($(ABCEXTERNAL),)
+ABCOPT="-A $(ABCEXTERNAL)"
+else
+ABCOPT=""
+endif
+
 test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/simple && bash run-test.sh $(SEEDOPT)
 	+cd tests/hana && bash run-test.sh $(SEEDOPT)
@@ -674,13 +680,13 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/share && bash run-test.sh $(SEEDOPT)
 	+cd tests/fsm && bash run-test.sh $(SEEDOPT)
 	+cd tests/techmap && bash run-test.sh
-	+cd tests/memories && bash run-test.sh $(SEEDOPT)
+	+cd tests/memories && bash run-test.sh $(ABCOPT) $(SEEDOPT)
 	+cd tests/bram && bash run-test.sh $(SEEDOPT)
 	+cd tests/various && bash run-test.sh
 	+cd tests/sat && bash run-test.sh
 	+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
 	+cd tests/opt && bash run-test.sh
-	+cd tests/aiger && bash run-test.sh
+	+cd tests/aiger && bash run-test.sh $(ABCOPT)
 	+cd tests/arch && bash run-test.sh
 	@echo ""
 	@echo "  Passed \"make test\"."
diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index 5246c1b48..deaf48a3d 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -2,6 +2,16 @@
 
 set -e
 
+OPTIND=1
+abcprog="../../yosys-abc"    # default to built-in version of abc
+while getopts "A:" opt
+do
+    case "$opt" in
+	A) abcprog="$OPTARG" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
 # NB: *.aag and *.aig must contain a symbol table naming the primary
 #     inputs and outputs, otherwise ABC and Yosys will name them
 #     arbitrarily (and inconsistently with each other).
@@ -11,7 +21,7 @@ for aag in *.aag; do
     # (which would have been created by the reference aig2aig utility,
     #  available from http://fmv.jku.at/aiger/)
     echo "Checking $aag."
-    ../../yosys-abc -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
+    $abcprog -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
     ../../yosys -qp "
 read_verilog ${aag%.*}_ref.v
 prep
@@ -28,7 +38,7 @@ done
 
 for aig in *.aig; do
     echo "Checking $aig."
-    ../../yosys-abc -q "read -c $aig; write ${aig%.*}_ref.v"
+    $abcprog -q "read -c $aig; write ${aig%.*}_ref.v"
     ../../yosys -qp "
 read_verilog ${aig%.*}_ref.v
 prep
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index d0537bb98..76acaa9cd 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -4,15 +4,17 @@ set -e
 
 OPTIND=1
 seed=""    # default to no seed specified
-while getopts "S:" opt
+abcopt=""
+while getopts "A:S:" opt
 do
     case "$opt" in
+	A) abcopt="-A $OPTARG" ;;
 	S) seed="-S $OPTARG" ;;
     esac
 done
 shift "$((OPTIND-1))"
 
-bash ../tools/autotest.sh $seed -G *.v
+bash ../tools/autotest.sh $abcopt $seed -G *.v
 
 for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 	echo -n "Testing expectations for $f .."
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 96d9cdda9..7b64b357f 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -23,12 +23,13 @@ warn_iverilog_git=false
 # The tests are skipped if firrtl2verilog is the empty string (the default).
 firrtl2verilog=""
 xfirrtl="../xfirrtl"
+abcprog="$toolsdir/../../yosys-abc"
 
 if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
 	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
@@ -65,6 +66,8 @@ while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
 			include_opts="$include_opts -I $OPTARG"
 			xinclude_opts="$xinclude_opts -i $OPTARG"
 			minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
+		A)
+			abcprog="$OPTARG" ;;
 		-)
 			case "${OPTARG}" in
 			    xfirrtl)
@@ -147,7 +150,7 @@ do
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
 		elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
-			"$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.${refext}"
+			$abcprog -c "read_aiger ../${fn}; write ${bn}_ref.${refext}"
 		else
 			refext=$ext
 			cp ../${fn} ${bn}_ref.${refext}

From fc87c010c504863b242b8882c1170396a7d1d43c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 14:18:56 -0700
Subject: [PATCH 005/111] autotest.sh to define _AUTOTB when test_autotb

---
 tests/tools/autotest.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 7b64b357f..4d3478628 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -157,7 +157,7 @@ do
 		fi
 
 		if [ ! -f ../${bn}_tb.v ]; then
-			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext}
+			"$toolsdir"/../../yosys -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext}
 		else
 			cp ../${bn}_tb.v ${bn}_tb.v
 		fi

From 7b298479d4a10ac20379955fa749e70560b72b7f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 2 Jul 2019 11:36:26 +0200
Subject: [PATCH 006/111] Fix read_verilog assert/assume/etc on default case
 label, fixes YosysHQ/SymbiYosys#53

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_lexer.l | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index d3fd91473..951d9c66f 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END
     to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some
     global state.. its a mess) */
 [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] {
+	if (!strcmp(yytext, "default"))
+		return TOK_DEFAULT;
 	frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 	return TOK_SVA_LABEL;
 }

From 4b49c0201edc37d0d3edd906e2693d6284a1b0ba Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 2 Jul 2019 16:47:54 +0100
Subject: [PATCH 007/111] Merge pull request #1153 from
 YosysHQ/dave/fix_multi_mux

memory_dff: Fix checking of feedback mux input when more than one mux
---
 passes/memory/memory_dff.cc   |  8 +++++---
 tests/memories/read_two_mux.v | 16 ++++++++++++++++
 tests/memories/run-test.sh    |  4 ++++
 3 files changed, 25 insertions(+), 3 deletions(-)
 create mode 100644 tests/memories/read_two_mux.v

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 5215cce44..32b97f27a 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -17,6 +17,7 @@
  *
  */
 
+#include <algorithm>
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 
@@ -183,12 +184,12 @@ struct MemoryDffWorker
 		if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data))
 		{
 			RTLIL::SigSpec en;
-			RTLIL::SigSpec check_q;
+			std::vector<RTLIL::SigSpec> check_q;
 
 			do {
 				bool enable_invert = mux_cells_a.count(sig_data) != 0;
 				Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
-				check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"));
+				check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")));
 				sig_data = sigmap(mux->getPort("\\Y"));
 				en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
 			} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
@@ -197,7 +198,8 @@ struct MemoryDffWorker
 				if (sigbit_users_count[bit] > 1)
 					goto skip_ff_after_read_merging;
 
-			if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q)
+			if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) &&
+					std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; }))
 			{
 				disconnect_dff(sig_data);
 				cell->setPort("\\CLK", clk_data);
diff --git a/tests/memories/read_two_mux.v b/tests/memories/read_two_mux.v
new file mode 100644
index 000000000..4f2e7e1cd
--- /dev/null
+++ b/tests/memories/read_two_mux.v
@@ -0,0 +1,16 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-no-rd-clk
+
+module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
+
+reg [7:0] bram[0:255];
+(* keep *) reg dummy;
+
+always @(posedge clk) begin
+	rdata <= re ? (reset ? 8'b0 : bram[addr]) : rdata;
+	if (we)
+		bram[addr] <= wdata;
+end
+
+endmodule
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index 76acaa9cd..8d1a8b413 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -31,6 +31,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 		grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected read clock."; false; }
 	fi
+	if grep -q expect-no-rd-clk $f; then
+		grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Expected no read clock."; false; }
+	fi
 	echo " ok."
 done
 

From d105e2f03f259e4f2be3d6d9ba970565d8422b87 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 3 Jul 2019 10:45:29 +0200
Subject: [PATCH 008/111] Merge pull request #1154 from
 whitequark/manual-sync-always

manual: explain the purpose of `sync always`
---
 manual/CHAPTER_Overview.tex | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 1a25c477f..3009bf2c0 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -331,8 +331,9 @@ to update {\tt \textbackslash{}q}.
 An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and
 exactly one RTLIL::CaseRule object, which is called the {\it root case}.
 
-An RTLIL::SyncRule object contains an (optional) synchronization condition
-(signal and edge-type) and zero or more assignments (RTLIL::SigSig).
+An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type) and zero or
+more assignments (RTLIL::SigSig). The {\tt always} synchronization condition is used to break combinatorial
+loops when a latch should be inferred instead.
 
 An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig)
 and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a

From fecd3aa2b15a20fc72d790b2437ee016ae879c14 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 3 Jul 2019 12:30:37 +0200
Subject: [PATCH 009/111] Merge pull request #1147 from
 YosysHQ/clifford/fix1144

Improve specify dummy parser
---
 frontends/verilog/verilog_parser.y | 95 +++++-------------------------
 tests/various/specify.v            | 11 +++-
 tests/various/specify.ys           |  2 +
 3 files changed, 26 insertions(+), 82 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index d89b2dc88..0fec445fa 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1021,13 +1021,8 @@ list_of_specparam_assignments:
 specparam_assignment:
 	ignspec_id '=' constant_mintypmax_expression ;
 
-/*
-pulsestyle_declaration :
-	;
-
-showcancelled_declaration :
-	;
-*/
+ignspec_opt_cond:
+	TOK_IF '(' ignspec_expr ')' | /* empty */;
 
 path_declaration :
 	simple_path_declaration ';'
@@ -1036,8 +1031,8 @@ path_declaration :
 	;
 
 simple_path_declaration :
-	parallel_path_description '=' path_delay_value |
-	full_path_description '=' path_delay_value
+	ignspec_opt_cond parallel_path_description '=' path_delay_value |
+	ignspec_opt_cond full_path_description '=' path_delay_value
 	;
 
 path_delay_value :
@@ -1047,32 +1042,20 @@ path_delay_value :
 	;
 
 list_of_path_delay_extra_expressions :
-/*
-	t_path_delay_expression
-	| trise_path_delay_expression ',' tfall_path_delay_expression
-	| trise_path_delay_expression ',' tfall_path_delay_expression ',' tz_path_delay_expression
-	| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
-	  tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression
-	| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
-	  tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression ','
-	  t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
-	  tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
-*/
-	',' path_delay_expression
-	|  ',' path_delay_expression ',' path_delay_expression
-	|  ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	|  ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
-	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	;
+	',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions;
+
+specify_edge_identifier :
+	TOK_POSEDGE | TOK_NEGEDGE ;
 
 parallel_path_description :
-	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
+	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
+	'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
+	'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
 
 full_path_description :
-	'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ;
+	'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
+	'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
+	'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
 
 // This was broken into 2 rules to solve shift/reduce conflicts
 list_of_path_inputs :
@@ -1112,56 +1095,6 @@ system_timing_args :
 	system_timing_arg |
 	system_timing_args ',' system_timing_arg ;
 
-/*
-t_path_delay_expression :
-	path_delay_expression;
-
-trise_path_delay_expression :
-	path_delay_expression;
-
-tfall_path_delay_expression :
-	path_delay_expression;
-
-tz_path_delay_expression :
-	path_delay_expression;
-
-t01_path_delay_expression :
-	path_delay_expression;
-
-t10_path_delay_expression :
-	path_delay_expression;
-
-t0z_path_delay_expression :
-	path_delay_expression;
-
-tz1_path_delay_expression :
-	path_delay_expression;
-
-t1z_path_delay_expression :
-	path_delay_expression;
-
-tz0_path_delay_expression :
-	path_delay_expression;
-
-t0x_path_delay_expression :
-	path_delay_expression;
-
-tx1_path_delay_expression :
-	path_delay_expression;
-
-t1x_path_delay_expression :
-	path_delay_expression;
-
-tx0_path_delay_expression :
-	path_delay_expression;
-
-txz_path_delay_expression :
-	path_delay_expression;
-
-tzx_path_delay_expression :
-	path_delay_expression;
-*/
-
 path_delay_expression :
 	ignspec_constant_expression;
 
diff --git a/tests/various/specify.v b/tests/various/specify.v
index afc421da8..5d44d78f7 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -7,9 +7,11 @@ module test (
 		if (EN) Q <= D;
 
 	specify
-		if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
+`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
+		if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
 		$setup(D, posedge CLK &&& EN, 5);
 		$hold(posedge CLK, D &&& EN, 6);
+`endif
 	endspecify
 endmodule
 
@@ -28,3 +30,10 @@ module test2 (
 		(B => Q) = 1.5;
 	endspecify
 endmodule
+
+module issue01144(input clk, d, output q);
+specify
+  (posedge clk => (q +: d)) = (3,1);
+  (posedge clk *> (q +: d)) = (3,1);
+endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index a5ca07219..00597e1e2 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -54,3 +54,5 @@ equiv_struct
 equiv_induct -seq 5
 equiv_status -assert
 design -reset
+
+read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v

From 17e0cc010c12fc69fdadc2c342da1ef8e16a2d91 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 5 Jul 2019 11:57:41 +0200
Subject: [PATCH 010/111] Merge pull request #1159 from
 btut/fix/1090_segfault_cell_and_wire

Throw runtime exception when trying to convert inexistend C++ object to Python
---
 misc/py_wrap_generator.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py
index 9e5727499..66d661fa1 100644
--- a/misc/py_wrap_generator.py
+++ b/misc/py_wrap_generator.py
@@ -779,6 +779,9 @@ class WClass:
 
 			#if self.link_type != link_types.pointer:
 			text += "\n\t\tstatic " + self.name + "* get_py_obj(" + long_name + "* ref)\n\t\t{"
+			text += "\n\t\t\tif(ref == nullptr){"
+			text += "\n\t\t\t\tthrow std::runtime_error(\"" + self.name + " does not exist.\");"
+			text += "\n\t\t\t}"
 			text += "\n\t\t\t" + self.name + "* ret = (" + self.name + "*)malloc(sizeof(" + self.name + "));"
 			if self.link_type == link_types.pointer:
 				text += "\n\t\t\tret->ref_obj = ref;"

From 76f20492a468ffef9902712e36c856f3a6e63dd5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 9 Jul 2019 16:56:29 +0200
Subject: [PATCH 011/111] Merge pull request #1162 from
 whitequark/rtlil-case-attrs

Allow attributes on individual switch cases in RTLIL
---
 backends/ilang/ilang_backend.cc |  5 +++++
 frontends/ilang/ilang_parser.y  | 13 +++++++++----
 kernel/rtlil.h                  |  2 +-
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index b4ba2b03f..313af7d5c 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -204,6 +204,11 @@ void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const
 
 	for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it)
 	{
+		for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) {
+			f << stringf("%s  attribute %s ", indent.c_str(), ait->first.c_str());
+			dump_const(f, ait->second);
+			f << stringf("\n");
+		}
 		f << stringf("%s  case ", indent.c_str());
 		for (size_t i = 0; i < (*it)->compare.size(); i++) {
 			if (i > 0)
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index 44c99906a..b4b9693da 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -282,14 +282,14 @@ proc_stmt:
 	} case_body sync_list TOK_END EOL;
 
 switch_stmt:
-	attr_list TOK_SWITCH sigspec EOL {
+	TOK_SWITCH sigspec EOL {
 		RTLIL::SwitchRule *rule = new RTLIL::SwitchRule;
-		rule->signal = *$3;
+		rule->signal = *$2;
 		rule->attributes = attrbuf;
 		switch_stack.back()->push_back(rule);
 		attrbuf.clear();
-		delete $3;
-	} switch_body TOK_END EOL;
+		delete $2;
+	} attr_list switch_body TOK_END EOL;
 
 attr_list:
 	/* empty */ |
@@ -298,9 +298,11 @@ attr_list:
 switch_body:
 	switch_body TOK_CASE {
 		RTLIL::CaseRule *rule = new RTLIL::CaseRule;
+		rule->attributes = attrbuf;
 		switch_stack.back()->back()->cases.push_back(rule);
 		switch_stack.push_back(&rule->switches);
 		case_stack.push_back(rule);
+		attrbuf.clear();
 	} compare_list EOL case_body {
 		switch_stack.pop_back();
 		case_stack.pop_back();
@@ -319,12 +321,15 @@ compare_list:
 	/* empty */;
 
 case_body:
+	case_body attr_stmt |
 	case_body switch_stmt |
 	case_body assign_stmt |
 	/* empty */;
 
 assign_stmt:
 	TOK_ASSIGN sigspec sigspec EOL {
+		if (attrbuf.size() != 0)
+			rtlil_frontend_ilang_yyerror("dangling attribute");
 		case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3));
 		delete $2;
 		delete $3;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 8509670ff..7b7367fba 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1315,7 +1315,7 @@ public:
 #endif
 };
 
-struct RTLIL::CaseRule
+struct RTLIL::CaseRule : public RTLIL::AttrObject
 {
 	std::vector<RTLIL::SigSpec> compare;
 	std::vector<RTLIL::SigSig> actions;

From 8af7ced5cd452bd0ef1e6bc17206e9360a893e49 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 9 Jul 2019 16:57:16 +0200
Subject: [PATCH 012/111] Merge pull request #1163 from
 whitequark/more-case-attrs

More support for case rule attributes
---
 backends/verilog/verilog_backend.cc | 17 +++++++++++------
 frontends/ast/genrtlil.cc           |  1 +
 passes/proc/proc_mux.cc             | 26 ++++++++++++++++----------
 3 files changed, 28 insertions(+), 16 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 827af5d85..6288502a5 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -364,20 +364,22 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 	}
 }
 
-void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false)
+void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false, bool as_comment = false)
 {
 	if (noattr)
 		return;
+	if (attr2comment)
+		as_comment = true;
 	for (auto it = attributes.begin(); it != attributes.end(); ++it) {
-		f << stringf("%s" "%s %s", indent.c_str(), attr2comment ? "/*" : "(*", id(it->first).c_str());
+		f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str());
 		f << stringf(" = ");
 		if (modattr && (it->second == Const(0, 1) || it->second == Const(0)))
 			f << stringf(" 0 ");
 		else if (modattr && (it->second == Const(1, 1) || it->second == Const(1)))
 			f << stringf(" 1 ");
 		else
-			dump_const(f, it->second, -1, 0, false, attr2comment);
-		f << stringf(" %s%c", attr2comment ? "*/" : "*)", term);
+			dump_const(f, it->second, -1, 0, false, as_comment);
+		f << stringf(" %s%c", as_comment ? "*/" : "*)", term);
 	}
 }
 
@@ -1492,6 +1494,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 		return;
 	}
 
+	dump_attributes(f, indent, sw->attributes);
 	f << stringf("%s" "casez (", indent.c_str());
 	dump_sigspec(f, sw->signal);
 	f << stringf(")\n");
@@ -1511,7 +1514,9 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 				dump_sigspec(f, (*it)->compare[i]);
 			}
 		}
-		f << stringf(":\n");
+		f << stringf(":");
+		dump_attributes(f, indent, (*it)->attributes, ' ', /*modattr=*/false, /*as_comment=*/true);
+		f << stringf("\n");
 		dump_case_body(f, indent + "    ", *it);
 	}
 
@@ -1662,7 +1667,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		}
 	}
 
-	dump_attributes(f, indent, module->attributes, '\n', true);
+	dump_attributes(f, indent, module->attributes, '\n', /*attr2comment=*/true);
 	f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
 	bool keep_running = true;
 	for (int port_id = 1; keep_running; port_id++) {
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 079fc11e5..571ddd988 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -504,6 +504,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 					RTLIL::CaseRule *backup_case = current_case;
 					current_case = new RTLIL::CaseRule;
+					current_case->attributes["\\src"] = stringf("%s:%d", child->filename.c_str(), child->linenum);
 					last_generated_case = current_case;
 					addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
 					for (auto node : child->children) {
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index aac0b121c..d029282fd 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -144,7 +144,13 @@ struct SnippetSwCache
 	}
 };
 
-RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, bool ifxmode)
+void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs)
+{
+	cell->attributes = sw->attributes;
+	cell->add_strpool_attribute("\\src", cs->get_strpool_attribute("\\src"));
+}
+
+RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
 {
 	std::stringstream sstr;
 	sstr << "$procmux$" << (autoidx++);
@@ -173,7 +179,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 		{
 			// create compare cell
 			RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? "$eqx" : "$eq");
-			eq_cell->attributes = sw->attributes;
+			apply_attrs(eq_cell, sw, cs);
 
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0);
@@ -199,7 +205,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 
 		// reduce cmp vector to one logic signal
 		RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or");
-		any_cell->attributes = sw->attributes;
+		apply_attrs(any_cell, sw, cs);
 
 		any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 		any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
@@ -212,7 +218,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 	return RTLIL::SigSpec(ctrl_wire);
 }
 
-RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, bool ifxmode)
+RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
 {
 	log_assert(when_signal.size() == else_signal.size());
 
@@ -224,7 +230,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 		return when_signal;
 
 	// compare results
-	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, ifxmode);
+	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
 	if (ctrl_sig.size() == 0)
 		return when_signal;
 	log_assert(ctrl_sig.size() == 1);
@@ -234,7 +240,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 
 	// create the multiplexer itself
 	RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux");
-	mux_cell->attributes = sw->attributes;
+	apply_attrs(mux_cell, sw, cs);
 
 	mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
 	mux_cell->setPort("\\A", else_signal);
@@ -246,7 +252,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
 	return RTLIL::SigSpec(result_wire);
 }
 
-void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, bool ifxmode)
+void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
 {
 	log_assert(last_mux_cell != NULL);
 	log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size());
@@ -254,7 +260,7 @@ void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::ve
 	if (when_signal == last_mux_cell->getPort("\\A"))
 		return;
 
-	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, ifxmode);
+	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
 	log_assert(ctrl_sig.size() == 1);
 	last_mux_cell->type = "$pmux";
 
@@ -395,9 +401,9 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
 			RTLIL::CaseRule *cs2 = sw->cases[case_idx];
 			RTLIL::SigSpec value = signal_to_mux_tree(mod, swcache, swpara, cs2, sig, initial_val, ifxmode);
 			if (last_mux_cell && pgroups[case_idx] == pgroups[case_idx+1])
-				append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, ifxmode);
+				append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, cs2, ifxmode);
 			else
-				result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, ifxmode);
+				result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, cs2, ifxmode);
 		}
 	}
 

From c8979a3353c531884fd7f7dec8c06682d0b4b3ec Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 9 Jul 2019 18:51:23 +0100
Subject: [PATCH 013/111] Update CHANGELOG

Signed-off-by: David Shah <dave@ds0.me>
---
 CHANGELOG | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG b/CHANGELOG
index 03ab2a7cc..b3a697562 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -28,6 +28,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "synth_ecp5 -nowidelut"
     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
+    - Added support for attributes on case rules
 
 
 Yosys 0.7 .. Yosys 0.8

From 1d58bbb79c36d88c24008797947789d9ae5605be Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 9 Jul 2019 22:51:25 +0200
Subject: [PATCH 014/111] Merge pull request #1175 from
 whitequark/write_verilog-fix-case-attr-position

write_verilog: fix placement of case attributes
---
 backends/verilog/verilog_backend.cc | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6288502a5..087c6fec6 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1501,6 +1501,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 
 	bool got_default = false;
 	for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
+		dump_attributes(f, indent + "  ", (*it)->attributes, '\n', /*modattr=*/false, /*as_comment=*/true);
 		if ((*it)->compare.size() == 0) {
 			if (got_default)
 				continue;
@@ -1514,9 +1515,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 				dump_sigspec(f, (*it)->compare[i]);
 			}
 		}
-		f << stringf(":");
-		dump_attributes(f, indent, (*it)->attributes, ' ', /*modattr=*/false, /*as_comment=*/true);
-		f << stringf("\n");
+		f << stringf(":\n");
 		dump_case_body(f, indent + "    ", *it);
 	}
 

From 82a29720684dc8db452289321340bf6e78dcbd2c Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 26 Jul 2019 16:45:51 +0100
Subject: [PATCH 015/111] Update CHANGELOG

Signed-off-by: David Shah <dave@ds0.me>
---
 CHANGELOG | 111 +++++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 101 insertions(+), 10 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index b3a697562..afbcffa26 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,33 +3,124 @@ List of major changes and improvements between releases
 =======================================================
 
 
-Yosys 0.8 .. Yosys 0.8-dev
+Yosys 0.8 .. Yosys 0.9
 --------------------------
 
  * Various
-    - Added $changed support to read_verilog
+    - Many bugfixes and small improvements
+    - Added support for SystemVerilog interfaces and modports
     - Added "write_edif -attrprop"
-    - Added "ice40_unlut" pass
     - Added "opt_lut" pass
-    - Added "synth_ice40 -relut"
-    - Added "synth_ice40 -noabc"
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
-    - Added "shregmap -tech xilinx"
+    - Added "flowmap" LUT mapping pass
+    - Added "rename -wire" to rename cells based on the wires they drive
+    - Added "bugpoint" for creating minimised testcases
+    - Added "write_edif -gndvccy"
+    - "write_verilog" to escape Verilog keywords
+    - Fixed sign handling of real constants
+    - "write_verilog" to write initial statement for initial flop state
+    - Added pmgen pattern matcher generator
+    - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
+    - Added "setundef -params" to replace undefined cell parameters
+    - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
+    - Fixed handling of defparam when default_nettype is none
+    - Fixed "wreduce" flipflop handling
+    - Fixed FIRRTL to Verilog process instance subfield assignment
+    - Added "write_verilog -siminit"
+    - Several fixes and improvements for mem2reg memories
+    - Fixed handling of task output ports in clocked always blocks
+    - Improved handling of and-with-1 and or-with-0 in "opt_expr"
     - Added "read_aiger" frontend
+    - Added "mutate" pass
+    - Added "hdlname" attribute
+    - Added "rename -output"
+    - Added "read_ilang -lib"
+    - Improved "proc" full_case detection and handling
+    - Added "whitebox" and "lib_whitebox" attributes
+    - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
+    - Added Python bindings and support for Python plug-ins
+    - Added "pmux2shiftx"
+    - Added log_debug framework for reduced default verbosity
+    - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
+    - Added "peepopt" peephole optimisation pass using pmgen
+    - Added approximate support for SystemVerilog "var" keyword
+    - Added parsing of "specify" blocks into $specrule and $specify[23]
+    - Added support for attributes on parameters and localparams
+    - Added support for parsing attributes on port connections
+    - Added "wreduce -keepdc"
+    - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
+    - Added Verilog wand/wor wire type support
+    - Added support for elaboration system tasks
     - Added "muxcover -mux{4,8,16}=<cost>"
     - Added "muxcover -dmux=<cost>"
     - Added "muxcover -nopartial"
     - Added "muxpack" pass
     - Added "pmux2shiftx -norange"
+    - Added support for "~" in filename parsing
+    - Added "read_verilog -pwires" feature to turn parameters into wires
+    - Fixed sign extension of unsized constants with 'bx and 'bz MSB
+    - Fixed genvar to be a signed type
+    - Added support for attributes on case rules
+    - Added "upto" and "offset" to JSON frontend and backend
+    - Several liberty file parser improvements
+    - Fixed handling of more complex BRAM patterns
+    - Add "write_aiger -I -O -B"
+
+ * Formal Verification
+    - Added $changed support to read_verilog
+    - Added "read_verilog -noassert -noassume -assert-assumes"
+    - Added btor ops for $mul, $div, $mod and $concat
+    - Added yosys-smtbmc support for btor witnesses
+    - Added "supercover" pass
+    - Fixed $global_clock handling vs autowire
+    - Added $dffsr support to "async2sync"
+    - Added "fmcombine" pass
+    - Added memory init support in "write_btor"
+    - Added "cutpoint" pass
+    - Changed "ne" to "neq" in btor2 output
+    - Added support for SVA "final" keyword
+    - Added "fmcombine -initeq -anyeq"
+    - Added timescale and generated-by header to yosys-smtbmc vcd output
+    - Improved BTOR2 handling of undriven wires
+
+ * Verific support
+    - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
+    - Improved support for asymmetric memories
+    - Added "verific -chparam"
+    - Fixed "verific -extnets" for more complex situations
+    - Added "read -verific" and "read -noverific"
+    - Added "hierarchy -chparam"
+
+ * New back-ends
+    - Added initial Anlogic support
+    - Added initial SmartFusion2 and IGLOO2 support
+
+ * ECP5 support
+    - Added "synth_ecp5 -nowidelut"
+    - Added BRAM inference support to "synth_ecp5"
+    - Added support for transforming Diamond IO and flipflop primitives
+
+ * iCE40 support
+    - Added "ice40_unlut" pass
+    - Added "synth_ice40 -relut"
+    - Added "synth_ice40 -noabc"
+    - Added "synth_ice40 -dffe_min_ce_use"
+    - Added DSP inference support using pmgen
+    - Added support for initialising BRAM primitives from a file
+    - Added iCE40 Ultra RGB LED driver cells
+
+ * Xilinx support 
+    - Use "write_edif -pvector bra" for Xilinx EDIF files
+    - Fixes for VPR place and route support with "synth_xilinx"
+    - Added more cell simulation models
+    - Added "synth_xilinx -family"
+    - Added "stat -tech xilinx" to estimate logic cell usage
     - Added "synth_xilinx -nocarry"
     - Added "synth_xilinx -nowidelut"
-    - Added "synth_ecp5 -nowidelut"
     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
-    - Fixed sign extension of unsized constants with 'bx and 'bz MSB
-    - Added support for attributes on case rules
-
+    - Added support for mapping RAM32X1D
 
 Yosys 0.7 .. Yosys 0.8
 ----------------------

From e9c5f1b3467d4566978dfb07c3b1fa91e94ef761 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 31 Jul 2019 11:49:48 +0200
Subject: [PATCH 016/111] Fix formatting for msys2 mingw build using GetSize

---
 Makefile                                   |  2 ++
 misc/launcher.c                            |  3 ++-
 passes/opt/opt_lut.cc                      |  8 ++++----
 passes/opt/rmports.cc                      |  2 +-
 passes/techmap/flowmap.cc                  | 10 +++++-----
 techlibs/anlogic/anlogic_determine_init.cc |  4 ++--
 techlibs/anlogic/anlogic_eqn.cc            |  4 ++--
 techlibs/gowin/determine_init.cc           |  4 ++--
 8 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/Makefile b/Makefile
index bbae8c159..d3b5b8fa6 100644
--- a/Makefile
+++ b/Makefile
@@ -861,9 +861,11 @@ config-mxe: clean
 
 config-msys2: clean
 	echo 'CONFIG := msys2' > Makefile.conf
+	echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
 
 config-msys2-64: clean
 	echo 'CONFIG := msys2-64' > Makefile.conf
+	echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
 
 config-cygwin: clean
 	echo 'CONFIG := cygwin' > Makefile.conf
diff --git a/misc/launcher.c b/misc/launcher.c
index 157d68cf3..e0d8208f1 100644
--- a/misc/launcher.c
+++ b/misc/launcher.c
@@ -61,6 +61,7 @@ SOFTWARE. */
 #include <windows.h>
 #include <tchar.h>
 #include <fcntl.h>
+#include <unistd.h>
 
 int child_pid=0;
 
@@ -338,7 +339,7 @@ int run(int argc, char **argv, int is_gui) {
 
     if (is_gui) {
         /* Use exec, we don't need to wait for the GUI to finish */
-        execv(ptr, (const char * const *)(newargs));
+        execv(ptr, (char * const *)(newargs));
         return fail("Could not exec %s", ptr);   /* shouldn't get here! */
     }
 
diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 26855fd70..dda10ec17 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -81,7 +81,7 @@ struct OptLutWorker
 			}
 		}
 
-		log("Number of LUTs: %8zu\n", luts.size());
+		log("Number of LUTs: %8d\n", GetSize(luts));
 		for (int arity = 1; arity <= max_arity; arity++)
 		{
 			if (arity_counts[arity])
@@ -353,14 +353,14 @@ struct OptLutWorker
 
 					int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
 					if (lutA_dlogic_inputs.size())
-						log("  Cell A is a %d-LUT with %zu dedicated connections. ", lutA_arity, lutA_dlogic_inputs.size());
+						log("  Cell A is a %d-LUT with %d dedicated connections. ", lutA_arity, GetSize(lutA_dlogic_inputs));
 					else
 						log("  Cell A is a %d-LUT. ", lutA_arity);
 					if (lutB_dlogic_inputs.size())
-						log("Cell B is a %d-LUT with %zu dedicated connections.\n", lutB_arity, lutB_dlogic_inputs.size());
+						log("Cell B is a %d-LUT with %d dedicated connections.\n", lutB_arity, GetSize(lutB_dlogic_inputs));
 					else
 						log("Cell B is a %d-LUT.\n", lutB_arity);
-					log("  Cells share %zu input(s) and can be merged into one %d-LUT.\n", common_inputs.size(), lutM_arity);
+					log("  Cells share %d input(s) and can be merged into one %d-LUT.\n", GetSize(common_inputs), lutM_arity);
 
 					const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B;
 					int combine_mask = 0;
diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc
index fc1596ebf..32363dd68 100644
--- a/passes/opt/rmports.cc
+++ b/passes/opt/rmports.cc
@@ -171,7 +171,7 @@ struct RmportsPassPass : public Pass {
 			wire->port_output = false;
 			wire->port_id = 0;
 		}
-		log("Removed %zu unused ports.\n", unused_ports.size());
+		log("Removed %d unused ports.\n", GetSize(unused_ports));
 
 		// Re-number all of the wires that DO have ports still on them
 		for(size_t i=0; i<module->ports.size(); i++)
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index f5892a60e..96d0df5f8 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -783,7 +783,7 @@ struct FlowmapWorker
 		int depth = 0;
 		for (auto label : labels)
 			depth = max(depth, label.second);
-		log("Mapped to %zu LUTs with maximum depth %d.\n", lut_nodes.size(), depth);
+		log("Mapped to %d LUTs with maximum depth %d.\n", GetSize(lut_nodes), depth);
 
 		if (debug)
 		{
@@ -1195,7 +1195,7 @@ struct FlowmapWorker
 
 	bool relax_depth_for_bound(bool first, int depth_bound, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs)
 	{
-		size_t initial_count = lut_nodes.size();
+		int initial_count = GetSize(lut_nodes);
 
 		for (auto node : lut_nodes)
 		{
@@ -1215,7 +1215,7 @@ struct FlowmapWorker
 
 			if (potentials.empty())
 			{
-				log("  Relaxed to %zu (+%zu) LUTs.\n", lut_nodes.size(), lut_nodes.size() - initial_count);
+				log("  Relaxed to %d (+%d) LUTs.\n", GetSize(lut_nodes), GetSize(lut_nodes) - initial_count);
 				if (!first && break_num == 1)
 				{
 					log("  Design fully relaxed.\n");
@@ -1419,9 +1419,9 @@ struct FlowmapWorker
 			lut_area += lut_table.size();
 
 			if ((int)input_nodes.size() >= minlut)
-				log("  Packed into a %zu-LUT %s.%s.\n", input_nodes.size(), log_id(module), log_id(lut));
+				log("  Packed into a %d-LUT %s.%s.\n", GetSize(input_nodes), log_id(module), log_id(lut));
 			else
-				log("  Packed into a %zu-LUT %s.%s (implemented as %d-LUT).\n", input_nodes.size(), log_id(module), log_id(lut), minlut);
+				log("  Packed into a %d-LUT %s.%s (implemented as %d-LUT).\n", GetSize(input_nodes), log_id(module), log_id(lut), minlut);
 		}
 
 		for (auto node : mapped_nodes)
diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc
index 34b1d4f8a..c4089dac2 100644
--- a/techlibs/anlogic/anlogic_determine_init.cc
+++ b/techlibs/anlogic/anlogic_determine_init.cc
@@ -50,7 +50,7 @@ struct AnlogicDetermineInitPass : public Pass {
 
 		extra_args(args, args.size(), design);
 
-		size_t cnt = 0;
+		int cnt = 0;
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct AnlogicDetermineInitPass : public Pass {
 				}
 			}
 		}
-		log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+		log_header(design, "Updated %d cells with determined init value.\n", cnt);
 	}
 } AnlogicDetermineInitPass;
 
diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc
index 741bf04cc..070d39a20 100644
--- a/techlibs/anlogic/anlogic_eqn.cc
+++ b/techlibs/anlogic/anlogic_eqn.cc
@@ -69,7 +69,7 @@ struct AnlogicEqnPass : public Pass {
 
 		extra_args(args, args.size(), design);
 
-		size_t cnt = 0;
+		int cnt = 0;
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
@@ -106,7 +106,7 @@ struct AnlogicEqnPass : public Pass {
 				}
 			}
 		}
-		log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt);
+		log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt);
 	}
 } AnlogicEqnPass;
 
diff --git a/techlibs/gowin/determine_init.cc b/techlibs/gowin/determine_init.cc
index 991e5245a..d9a0880f6 100644
--- a/techlibs/gowin/determine_init.cc
+++ b/techlibs/gowin/determine_init.cc
@@ -50,7 +50,7 @@ struct DetermineInitPass : public Pass {
 
 		extra_args(args, args.size(), design);
 
-		size_t cnt = 0;
+		int cnt = 0;
 		for (auto module : design->selected_modules())
 		{
 			for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct DetermineInitPass : public Pass {
 				}
 			}
 		}
-		log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+		log_header(design, "Updated %d cells with determined init value.\n", cnt);
 	}
 } DetermineInitPass;
 

From bf59f31b4366e2e595821dc9b35f6082ff0d747c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 31 Jul 2019 17:30:48 +0200
Subject: [PATCH 017/111] New mxe hacks needed to support 2ca237e

---
 kernel/yosys.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/kernel/yosys.h b/kernel/yosys.h
index c7b671724..730efe825 100644
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -87,6 +87,10 @@ extern int Tcl_EvalFile(Tcl_Interp *interp, const char *fileName);
 extern void Tcl_Finalize(void);
 extern int Tcl_GetCommandInfo(Tcl_Interp *interp, const char *cmdName, Tcl_CmdInfo *infoPtr);
 extern const char *Tcl_GetStringResult(Tcl_Interp *interp);
+extern Tcl_Obj *Tcl_NewStringObj(const char *bytes, int length);
+extern Tcl_Obj *Tcl_NewIntObj(int intValue);
+extern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]);
+extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags);
 #  endif
 #endif
 

From ce0de937f4036e70b18afd765428288596fa0200 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 31 Jul 2019 17:31:07 +0200
Subject: [PATCH 018/111] Fix yosys linking for mxe

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index d3b5b8fa6..579fff007 100644
--- a/Makefile
+++ b/Makefile
@@ -394,7 +394,7 @@ endif
 
 ifeq ($(CONFIG),mxe)
 CXXFLAGS += -DYOSYS_ENABLE_TCL
-LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 -lz
+LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 -lz -luserenv
 else
 CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags tcl || echo -I$(TCL_INCLUDE)) -DYOSYS_ENABLE_TCL
 ifeq ($(OS), FreeBSD)

From 2ec5a3ec9248e86bb24f29253f1610aeff431e7d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 31 Jul 2019 18:02:27 +0200
Subject: [PATCH 019/111] Fix linking issue for new mxe and pthread

---
 Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 579fff007..89155fae8 100644
--- a/Makefile
+++ b/Makefile
@@ -260,7 +260,8 @@ CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
 LDLIBS := $(filter-out -lrt,$(LDLIBS))
 ABCMKARGS += ARCHFLAGS="-DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
-ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc"
+# TODO: Try to solve pthread linking issue in more appropriate way
+ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" LDFLAGS="-Wl,--allow-multiple-definition" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc"
 EXE = .exe
 
 else ifeq ($(CONFIG),msys2)

From 2b4e50ac3dd33ddf978eb4994985727338c61dff Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 31 Jul 2019 09:10:24 +0200
Subject: [PATCH 020/111] Visual Studio build fix

---
 passes/techmap/abc.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 5b19d84fb..bf05c68e7 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -49,6 +49,7 @@
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
+#include <cctype>
 #include <cerrno>
 #include <sstream>
 #include <climits>

From ab98f604fd1319e0f42b0c5dc8bb6be5d3d2ba38 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 3 Aug 2019 12:29:30 +0200
Subject: [PATCH 021/111] Initial EFINIX support

---
 techlibs/efinix/Makefile.inc    |   6 +
 techlibs/efinix/arith_map.v     |  78 ++++++++++++
 techlibs/efinix/cells_map.v     |  45 +++++++
 techlibs/efinix/cells_sim.v     |  36 ++++++
 techlibs/efinix/synth_efinix.cc | 205 ++++++++++++++++++++++++++++++++
 5 files changed, 370 insertions(+)
 create mode 100644 techlibs/efinix/Makefile.inc
 create mode 100644 techlibs/efinix/arith_map.v
 create mode 100644 techlibs/efinix/cells_map.v
 create mode 100644 techlibs/efinix/cells_sim.v
 create mode 100644 techlibs/efinix/synth_efinix.cc

diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc
new file mode 100644
index 000000000..3f3394c96
--- /dev/null
+++ b/techlibs/efinix/Makefile.inc
@@ -0,0 +1,6 @@
+
+OBJS += techlibs/efinix/synth_efinix.o
+
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v
new file mode 100644
index 000000000..ae955663c
--- /dev/null
+++ b/techlibs/efinix/arith_map.v
@@ -0,0 +1,78 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <miodrag@symbioticeda.com>
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$alu" *)
+module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH  = 1;
+	parameter B_WIDTH  = 1;
+	parameter Y_WIDTH  = 1;
+
+	input [A_WIDTH-1:0] A;
+	input [B_WIDTH-1:0] B;
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	output CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	wire [Y_WIDTH-1:0] AA = A_buf;
+	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+	wire [Y_WIDTH+1:0] COx;
+	wire [Y_WIDTH+2:0] C = {COx, CI};
+
+   EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
+   adder_cin  (
+        .I0(C[0]),
+        .I1(1'b1),
+        .CI(1'b0),
+        .CO(COx[0])
+	);
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
+      EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
+      adder_i (
+            .I0(AA[i]),
+            .I1(BB[i]),
+            .CI(C[i+1]),
+            .O(Y[i]),
+            .CO(COx[i+1])
+        );
+	  end: slice
+	endgenerate
+
+   EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))				
+   adder_cout  (
+      .I0(1'b0),
+      .I1(1'b0),
+      .CI(C[Y_WIDTH+1]),
+      .O(COx[Y_WIDTH+1])
+   );
+   assign CO = COx[Y_WIDTH+1];
+	/* End implementation */
+	assign X = AA ^ BB;
+endmodule
\ No newline at end of file
diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v
new file mode 100644
index 000000000..70c19635e
--- /dev/null
+++ b/techlibs/efinix/cells_map.v
@@ -0,0 +1,45 @@
+module  \$_DFF_N_ (input D, C, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+
+module  \$_DFFE_NN_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b0), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+module  \$_DFFE_NP_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+
+module  \$_DFFE_PN_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b0), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+
+module  \$_DFF_NN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+
+module  \$_DFF_NP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+
+`ifndef NO_LUT
+module \$lut (A, Y);
+  parameter WIDTH = 0;
+  parameter LUT = 0;
+
+  input [WIDTH-1:0] A;
+  output Y;
+
+  generate
+    if (WIDTH == 1) begin
+      EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
+    end else
+    if (WIDTH == 2) begin
+      EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
+    end else
+    if (WIDTH == 3) begin
+      EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
+    end else
+    if (WIDTH == 4) begin
+      EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+    end else begin
+      wire _TECHMAP_FAIL_ = 1;
+    end
+  endgenerate
+endmodule
+`endif
diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v
new file mode 100644
index 000000000..aaff955a2
--- /dev/null
+++ b/techlibs/efinix/cells_sim.v
@@ -0,0 +1,36 @@
+module EFX_LUT4(
+   output O, 
+   input I0,
+   input I1,
+   input I2,
+   input I3
+);
+   parameter LUTMASK  = 16'h0000;
+endmodule
+
+module EFX_ADD(
+   output O,
+   output CO,
+   input I0,
+   input I1,
+   input CI
+);
+   parameter I0_POLARITY   = 1;
+   parameter I1_POLARITY   = 1;
+endmodule
+
+module EFX_FF(
+   output Q,
+   input D,
+   input CE,
+   input CLK,
+   input SR
+);
+   parameter CLK_POLARITY = 1;
+   parameter CE_POLARITY = 1;
+   parameter SR_POLARITY = 1;
+   parameter SR_SYNC = 0;
+   parameter SR_VALUE = 0;
+   parameter SR_SYNC_PRIORITY = 0;
+   parameter D_POLARITY = 1;
+endmodule
\ No newline at end of file
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
new file mode 100644
index 000000000..9c644d363
--- /dev/null
+++ b/techlibs/efinix/synth_efinix.cc
@@ -0,0 +1,205 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2019  Miodrag Milanovic <miodrag@symbioticeda.com>
+ *  Copyright (C) 2019  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthEfinixPass : public ScriptPass
+{
+	SynthEfinixPass() : ScriptPass("synth_efinix", "synthesis for Efinix FPGAs") { }
+
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    synth_efinix [options]\n");
+		log("\n");
+		log("This command runs synthesis for Efinix FPGAs.\n");
+		log("\n");
+		log("    -top <module>\n");
+		log("        use the specified module as top module\n");
+		log("\n");
+		log("    -edif <file>\n");
+		log("        write the design to the specified EDIF file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -json <file>\n");
+		log("        write the design to the specified JSON file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        only run the commands between the labels (see below). an empty\n");
+		log("        from label is synonymous to 'begin', and empty to label is\n");
+		log("        synonymous to the end of the command list.\n");
+		log("\n");
+		log("    -noflatten\n");
+		log("        do not flatten design before synthesis\n");
+		log("\n");
+		log("    -retime\n");
+		log("        run 'abc' with -dff option\n");
+		log("\n");
+		log("\n");
+		log("The following commands are executed by this synthesis command:\n");
+		help_script();
+		log("\n");
+	}
+
+	string top_opt, edif_file, json_file;
+	bool flatten, retime;
+
+	void clear_flags() YS_OVERRIDE
+	{
+		top_opt = "-auto-top";
+		edif_file = "";
+		json_file = "";
+		flatten = true;
+		retime = false;
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		string run_from, run_to;
+		clear_flags();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-top" && argidx+1 < args.size()) {
+				top_opt = "-top " + args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+				edif_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-json" && argidx+1 < args.size()) {
+				json_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos+1);
+				continue;
+			}
+			if (args[argidx] == "-noflatten") {
+				flatten = false;
+				continue;
+			}
+			if (args[argidx] == "-retime") {
+				retime = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (!design->full_selection())
+			log_cmd_error("This command only operates on fully selected designs!\n");
+
+		log_header(design, "Executing SYNTH_EFINIX pass.\n");
+		log_push();
+
+		run_script(design, run_from, run_to);
+
+		log_pop();
+	}
+
+	void script() YS_OVERRIDE
+	{
+		if (check_label("begin"))
+		{
+			run("read_verilog -lib +/efinix/cells_sim.v");
+			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+		}
+
+		if (flatten && check_label("flatten", "(unless -noflatten)"))
+		{
+			run("proc");
+			run("flatten");
+			run("tribuf -logic");
+			run("deminout");
+		}
+
+		if (check_label("coarse"))
+		{
+			run("synth -run coarse");
+		}
+
+		if (check_label("fine"))
+		{
+			run("opt -fast -mux_undef -undriven -fine");
+			run("memory_map");
+			run("opt -undriven -fine");
+			run("techmap -map +/techmap.v -map +/efinix/arith_map.v");
+			if (retime || help_mode)
+				run("abc -dff", "(only if -retime)");
+		}
+
+		if (check_label("map_ffs"))
+		{
+			run("dffsr2dff");
+			run("techmap -D NO_LUT -map +/efinix/cells_map.v");
+			run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit");
+			run("opt_expr -mux_undef");
+			run("simplemap");
+		}
+
+		if (check_label("map_luts"))
+		{
+			run("abc -lut 4");
+			run("clean");
+		}
+
+		if (check_label("map_cells"))
+		{
+			run("techmap -map +/efinix/cells_map.v");
+			run("clean");
+		}
+
+		if (check_label("check"))
+		{
+			run("hierarchy -check");
+			run("stat");
+			run("check -noinit");
+		}
+
+		if (check_label("edif"))
+		{
+			if (!edif_file.empty() || help_mode)
+				run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
+		}
+
+		if (check_label("json"))
+		{
+			if (!json_file.empty() || help_mode)
+				run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+		}
+	}
+} SynthEfinixPass;
+
+PRIVATE_NAMESPACE_END

From 6e210f26fa97fa65c420534f0ec0e26eeb1b078a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 3 Aug 2019 14:40:23 +0200
Subject: [PATCH 022/111] Custom step to add global clock buffers

---
 techlibs/efinix/Makefile.inc    |   1 +
 techlibs/efinix/cells_sim.v     |  10 ++-
 techlibs/efinix/efinix_gbuf.cc  | 113 ++++++++++++++++++++++++++++++++
 techlibs/efinix/synth_efinix.cc |   6 ++
 4 files changed, 129 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/efinix/efinix_gbuf.cc

diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc
index 3f3394c96..82dfa3cd8 100644
--- a/techlibs/efinix/Makefile.inc
+++ b/techlibs/efinix/Makefile.inc
@@ -1,5 +1,6 @@
 
 OBJS += techlibs/efinix/synth_efinix.o
+OBJS += techlibs/efinix/efinix_gbuf.o
 
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v
index aaff955a2..2cbf8ae4b 100644
--- a/techlibs/efinix/cells_sim.v
+++ b/techlibs/efinix/cells_sim.v
@@ -33,4 +33,12 @@ module EFX_FF(
    parameter SR_VALUE = 0;
    parameter SR_SYNC_PRIORITY = 0;
    parameter D_POLARITY = 1;
-endmodule
\ No newline at end of file
+endmodule
+
+module EFX_GBUFCE (
+   input CE,
+   input I,
+   output O
+);
+   parameter CE_POLARITY = 1'b1;
+endmodule
diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc
new file mode 100644
index 000000000..50f84c30c
--- /dev/null
+++ b/techlibs/efinix/efinix_gbuf.cc
@@ -0,0 +1,113 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2019  Miodrag Milanovic <miodrag@symbioticeda.com>
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static void handle_gbufs(Module *module)
+{
+	SigMap sigmap(module);
+
+	pool<SigBit> clk_bits;
+	dict<SigBit, SigBit> rewrite_bits;
+	vector<pair<Cell*, SigBit>> pad_bits;
+
+	for (auto cell : module->cells())
+	{
+		if (cell->type == "\\EFX_FF") {
+			for (auto bit : sigmap(cell->getPort("\\CLK")))
+				clk_bits.insert(bit);
+		}
+	}
+
+	for (auto wire : vector<Wire*>(module->wires()))
+	{
+		if (!wire->port_input)
+			continue;
+
+		for (int index = 0; index < GetSize(wire); index++)
+		{
+			SigBit bit(wire, index);
+			SigBit canonical_bit = sigmap(bit);
+
+			if (!clk_bits.count(canonical_bit))
+				continue;
+
+			Cell *c = module->addCell(NEW_ID, "\\EFX_GBUFCE");
+			SigBit new_bit = module->addWire(NEW_ID);
+			c->setParam("\\CE_POLARITY", State::S1);
+			c->setPort("\\O", new_bit);
+			c->setPort("\\CE", State::S1);
+			pad_bits.push_back(make_pair(c, bit));
+			rewrite_bits[canonical_bit] = new_bit;
+
+			log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
+		}
+	}
+
+	auto rewrite_function = [&](SigSpec &s) {
+		for (auto &bit : s) {
+			SigBit canonical_bit = sigmap(bit);
+			if (rewrite_bits.count(canonical_bit))
+				bit = rewrite_bits.at(canonical_bit);
+		}
+	};
+
+	module->rewrite_sigspecs(rewrite_function);
+
+	for (auto &it : pad_bits)
+		it.first->setPort("\\I", it.second);
+}
+
+struct EfinixGbufPass : public Pass {
+	EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    efinix_gbuf [options] [selection]\n");
+		log("\n");
+		log("Add Efinix global clock buffers to top module as needed.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n");
+		
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		Module *module = design->top_module();
+
+		if (module == nullptr)
+			log_cmd_error("No top module found.\n");
+
+		handle_gbufs(module);		
+	}
+} EfinixGbufPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index 9c644d363..3f17bafa3 100644
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -181,6 +181,12 @@ struct SynthEfinixPass : public ScriptPass
 			run("clean");
 		}
 
+		if (check_label("map_gbuf"))
+		{
+			run("efinix_gbuf");
+			run("clean");
+		}
+		
 		if (check_label("check"))
 		{
 			run("hierarchy -check");

From cf96f41c6d9c405ddc039a8d0629731924b774ed Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 4 Aug 2019 11:46:36 +0200
Subject: [PATCH 023/111] Added bram support

---
 techlibs/efinix/Makefile.inc             |  3 +
 techlibs/efinix/bram.txt                 | 32 +++++++++
 techlibs/efinix/brams_map.v              | 65 +++++++++++++++++
 techlibs/efinix/cells_sim.v              | 65 ++++++++++++++++-
 techlibs/efinix/efinix_determine_init.cc | 89 ++++++++++++++++++++++++
 techlibs/efinix/synth_efinix.cc          |  7 ++
 6 files changed, 260 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/efinix/bram.txt
 create mode 100644 techlibs/efinix/brams_map.v
 create mode 100644 techlibs/efinix/efinix_determine_init.cc

diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc
index 82dfa3cd8..d0593baec 100644
--- a/techlibs/efinix/Makefile.inc
+++ b/techlibs/efinix/Makefile.inc
@@ -1,7 +1,10 @@
 
 OBJS += techlibs/efinix/synth_efinix.o
 OBJS += techlibs/efinix/efinix_gbuf.o
+OBJS += techlibs/efinix/efinix_determine_init.o
 
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt))
\ No newline at end of file
diff --git a/techlibs/efinix/bram.txt b/techlibs/efinix/bram.txt
new file mode 100644
index 000000000..0b3fd9308
--- /dev/null
+++ b/techlibs/efinix/bram.txt
@@ -0,0 +1,32 @@
+bram $__EFINIX_5K
+  init 1
+
+  abits 8  @a8d16
+  dbits 16 @a8d16
+  abits 9  @a9d8
+  dbits 8  @a9d8
+  abits 10 @a10d4
+  dbits 4  @a10d4
+  abits 11 @a11d2
+  dbits 2  @a11d2
+  abits 12 @a12d1
+  dbits 1  @a12d1
+  abits 8  @a8d20
+  dbits 20 @a8d20
+  abits 9  @a9d10
+  dbits 10 @a9d10
+
+  groups 2
+  ports 1 1
+  wrmode 1 0
+  enable 1 1
+  transp 0 2
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+match $__EFINIX_5K
+  min bits 256
+  min efficiency 5
+  shuffle_enable B
+endmatch
diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v
new file mode 100644
index 000000000..9ef01d026
--- /dev/null
+++ b/techlibs/efinix/brams_map.v
@@ -0,0 +1,65 @@
+module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+	parameter CFG_ABITS = 8;
+	parameter CFG_DBITS = 20;
+	parameter CFG_ENABLE_A = 2;
+
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+	parameter [5119:0] INIT = 5119'bx;
+	parameter TRANSP2 = 0;
+
+	input CLK2;
+	input CLK3;
+
+	input [CFG_ABITS-1:0] A1ADDR;
+	input [CFG_DBITS-1:0] A1DATA;
+	input [CFG_ENABLE_A-1:0] A1EN;
+
+	input [CFG_ABITS-1:0] B1ADDR;
+	output [CFG_DBITS-1:0] B1DATA;
+	input B1EN;
+
+	localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST";
+
+	EFX_RAM_5K #(
+   		.READ_WIDTH(20),
+   		.WRITE_WIDTH(20),
+   		.OUTPUT_REG(1'b0),
+   		.RCLK_POLARITY(1'b1),
+   		.RE_POLARITY(1'b1),
+   		.WCLK_POLARITY(1'b1),
+   		.WE_POLARITY(1'b1),
+   		.WCLKE_POLARITY(1'b1),
+   		.WRITE_MODE(WRITEMODE_A),
+		.INIT_0(INIT[ 0*256 +: 256]),
+		.INIT_1(INIT[ 1*256 +: 256]),
+		.INIT_2(INIT[ 2*256 +: 256]),
+		.INIT_3(INIT[ 3*256 +: 256]),
+		.INIT_4(INIT[ 4*256 +: 256]),
+		.INIT_5(INIT[ 5*256 +: 256]),
+		.INIT_6(INIT[ 6*256 +: 256]),
+		.INIT_7(INIT[ 7*256 +: 256]),
+		.INIT_8(INIT[ 8*256 +: 256]),
+		.INIT_9(INIT[ 9*256 +: 256]),
+		.INIT_A(INIT[10*256 +: 256]),
+		.INIT_B(INIT[11*256 +: 256]),
+		.INIT_C(INIT[12*256 +: 256]),
+		.INIT_D(INIT[13*256 +: 256]),
+		.INIT_E(INIT[14*256 +: 256]),
+		.INIT_F(INIT[15*256 +: 256]),
+		.INIT_10(INIT[16*256 +: 256]),
+		.INIT_11(INIT[17*256 +: 256]),
+		.INIT_12(INIT[18*256 +: 256]),
+		.INIT_13(INIT[19*256 +: 256])
+	) _TECHMAP_REPLACE_ (
+   		.WDATA(A1DATA),
+   		.WADDR(A1ADDR),
+   		.WE(A1EN),
+   		.WCLK(CLK2),
+   		.WCLKE(1'b1),
+   		.RDATA(B1DATA),
+   		.RADDR(B1ADDR),
+   		.RE(B1EN),
+   		.RCLK(CLK3)
+	);
+endmodule
diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v
index 2cbf8ae4b..8c8f6afaa 100644
--- a/techlibs/efinix/cells_sim.v
+++ b/techlibs/efinix/cells_sim.v
@@ -35,10 +35,73 @@ module EFX_FF(
    parameter D_POLARITY = 1;
 endmodule
 
-module EFX_GBUFCE (
+module EFX_GBUFCE(
    input CE,
    input I,
    output O
 );
    parameter CE_POLARITY = 1'b1;
 endmodule
+
+module EFX_RAM_5K(
+   input [WRITE_WIDTH-1:0] WDATA,
+   input [WRITE_ADDR_WIDTH-1:0] WADDR,
+   input WE, 
+   input WCLK,
+   input WCLKE, 
+   output [READ_WIDTH-1:0] RDATA, 
+   input [READ_ADDR_WIDTH-1:0] RADDR,
+   input RE, 
+   input RCLK
+);
+   parameter READ_WIDTH = 20;
+   parameter WRITE_WIDTH = 20;
+   parameter OUTPUT_REG = 1'b0;
+   parameter RCLK_POLARITY  = 1'b1;
+   parameter RE_POLARITY    = 1'b1;
+   parameter WCLK_POLARITY  = 1'b1;
+   parameter WE_POLARITY    = 1'b1;
+   parameter WCLKE_POLARITY = 1'b1;
+   parameter WRITE_MODE = "READ_FIRST";
+   parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+   parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+   localparam READ_ADDR_WIDTH = 
+			    (READ_WIDTH == 16) ? 8 :  // 256x16
+			    (READ_WIDTH == 8)  ? 9 :  // 512x8
+			    (READ_WIDTH == 4)  ? 10 : // 1024x4
+			    (READ_WIDTH == 2)  ? 11 : // 2048x2
+			    (READ_WIDTH == 1)  ? 12 : // 4096x1
+			    (READ_WIDTH == 20) ? 8 :  // 256x20
+			    (READ_WIDTH == 10) ? 9 :  // 512x10
+			    (READ_WIDTH == 5)  ? 10 : -1; // 1024x5
+   
+   localparam WRITE_ADDR_WIDTH = 
+			    (WRITE_WIDTH == 16) ? 8 :  // 256x16
+			    (WRITE_WIDTH == 8)  ? 9 :  // 512x8
+			    (WRITE_WIDTH == 4)  ? 10 : // 1024x4
+			    (WRITE_WIDTH == 2)  ? 11 : // 2048x2
+			    (WRITE_WIDTH == 1)  ? 12 : // 4096x1
+			    (WRITE_WIDTH == 20) ? 8 :  // 256x20
+			    (WRITE_WIDTH == 10) ? 9 :  // 512x10
+			    (WRITE_WIDTH == 5)  ? 10 : -1; // 1024x5
+   
+endmodule
\ No newline at end of file
diff --git a/techlibs/efinix/efinix_determine_init.cc b/techlibs/efinix/efinix_determine_init.cc
new file mode 100644
index 000000000..54da703ff
--- /dev/null
+++ b/techlibs/efinix/efinix_determine_init.cc
@@ -0,0 +1,89 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct EfinixDetermineInitPass : public Pass {
+	EfinixDetermineInitPass() : Pass("efinix_determine_init", "Efinix: Determine the init value of cells") { }
+	void help() YS_OVERRIDE
+	{
+		log("\n");
+		log("    efinix_determine_init [selection]\n");
+		log("\n");
+		log("Determine the init value of cells that doesn't allow unknown init value.\n");
+		log("\n");
+	}
+
+	Const determine_init(Const init)
+	{
+		for (int i = 0; i < GetSize(init); i++) {
+			if (init[i] != State::S0 && init[i] != State::S1)
+				init[i] = State::S0;
+		}
+
+		return init;
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing EFINIX_DETERMINE_INIT pass (determine init value for cells).\n");
+
+		extra_args(args, args.size(), design);
+
+		int cnt = 0;
+		for (auto module : design->selected_modules())
+		{
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type == "\\EFX_RAM_5K")
+				{
+					cell->setParam("\\INIT_0", determine_init(cell->getParam("\\INIT_0")));					
+					cell->setParam("\\INIT_1", determine_init(cell->getParam("\\INIT_1")));
+					cell->setParam("\\INIT_2", determine_init(cell->getParam("\\INIT_2")));
+					cell->setParam("\\INIT_3", determine_init(cell->getParam("\\INIT_3")));
+					cell->setParam("\\INIT_4", determine_init(cell->getParam("\\INIT_4")));
+					cell->setParam("\\INIT_5", determine_init(cell->getParam("\\INIT_5")));
+					cell->setParam("\\INIT_6", determine_init(cell->getParam("\\INIT_6")));
+					cell->setParam("\\INIT_7", determine_init(cell->getParam("\\INIT_7")));
+					cell->setParam("\\INIT_8", determine_init(cell->getParam("\\INIT_8")));
+					cell->setParam("\\INIT_9", determine_init(cell->getParam("\\INIT_9")));
+					cell->setParam("\\INIT_A", determine_init(cell->getParam("\\INIT_A")));
+					cell->setParam("\\INIT_B", determine_init(cell->getParam("\\INIT_B")));
+					cell->setParam("\\INIT_C", determine_init(cell->getParam("\\INIT_C")));
+					cell->setParam("\\INIT_D", determine_init(cell->getParam("\\INIT_D")));
+					cell->setParam("\\INIT_E", determine_init(cell->getParam("\\INIT_E")));
+					cell->setParam("\\INIT_F", determine_init(cell->getParam("\\INIT_F")));
+					cell->setParam("\\INIT_10", determine_init(cell->getParam("\\INIT_10")));
+					cell->setParam("\\INIT_11", determine_init(cell->getParam("\\INIT_11")));
+					cell->setParam("\\INIT_12", determine_init(cell->getParam("\\INIT_12")));
+					cell->setParam("\\INIT_13", determine_init(cell->getParam("\\INIT_13")));
+
+					cnt++;
+				}
+			}
+		}
+		log_header(design, "Updated %d cells with determined init value.\n", cnt);
+	}
+} EfinixDetermineInitPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index 3f17bafa3..000a17310 100644
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -150,6 +150,13 @@ struct SynthEfinixPass : public ScriptPass
 			run("synth -run coarse");
 		}
 
+		if (check_label("map_bram", "(skip if -nobram)"))
+		{
+			run("memory_bram -rules +/efinix/bram.txt");
+			run("techmap -map +/efinix/brams_map.v");
+			run("efinix_determine_init");
+		}
+
 		if (check_label("fine"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");

From 8a3329871ba7bab98982a101327b8375cd73344d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 4 Aug 2019 12:17:55 +0200
Subject: [PATCH 024/111] clock for ram trough gbuf

---
 techlibs/efinix/efinix_gbuf.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc
index 50f84c30c..e75fb3f4d 100644
--- a/techlibs/efinix/efinix_gbuf.cc
+++ b/techlibs/efinix/efinix_gbuf.cc
@@ -38,6 +38,12 @@ static void handle_gbufs(Module *module)
 			for (auto bit : sigmap(cell->getPort("\\CLK")))
 				clk_bits.insert(bit);
 		}
+		if (cell->type == "\\EFX_RAM_5K") {
+			for (auto bit : sigmap(cell->getPort("\\RCLK")))
+				clk_bits.insert(bit);
+			for (auto bit : sigmap(cell->getPort("\\WCLK")))
+				clk_bits.insert(bit);
+		}
 	}
 
 	for (auto wire : vector<Wire*>(module->wires()))

From d51b135e331326032b003934905c17750e116014 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 9 Aug 2019 12:37:10 +0200
Subject: [PATCH 025/111] Fix CO

---
 techlibs/efinix/arith_map.v | 50 ++++++++++++++++++-------------------
 1 file changed, 24 insertions(+), 26 deletions(-)

diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v
index ae955663c..ef903171f 100644
--- a/techlibs/efinix/arith_map.v
+++ b/techlibs/efinix/arith_map.v
@@ -31,7 +31,7 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
 	output [Y_WIDTH-1:0] X, Y;
 
 	input CI, BI;
-	output CO;
+	output [Y_WIDTH-1:0] CO;
 
 	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
 
@@ -41,38 +41,36 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
 
 	wire [Y_WIDTH-1:0] AA = A_buf;
 	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
-	wire [Y_WIDTH+1:0] COx;
-	wire [Y_WIDTH+2:0] C = {COx, CI};
+	wire [Y_WIDTH:0] C;
 
-   EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
-   adder_cin  (
-        .I0(C[0]),
+    EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
+    adder_cin  (
+        .I0(CI),
         .I1(1'b1),
         .CI(1'b0),
-        .CO(COx[0])
+        .CO(C[0])
 	);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
-      EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
-      adder_i (
-            .I0(AA[i]),
-            .I1(BB[i]),
-            .CI(C[i+1]),
-            .O(Y[i]),
-            .CO(COx[i+1])
-        );
-	  end: slice
+		EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
+		adder_i (
+			.I0(AA[i]),
+			.I1(BB[i]),
+			.CI(C[i]),
+			.O(Y[i]),
+			.CO(C[i+1])
+		);
+		EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))				
+		adder_cout  (
+			.I0(1'b0),
+			.I1(1'b0),
+			.CI(C[i+1]),
+			.O(CO[i])
+		);
+	  end: slice	  
 	endgenerate
 
-   EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))				
-   adder_cout  (
-      .I0(1'b0),
-      .I1(1'b0),
-      .CI(C[Y_WIDTH+1]),
-      .O(COx[Y_WIDTH+1])
-   );
-   assign CO = COx[Y_WIDTH+1];
-	/* End implementation */
-	assign X = AA ^ BB;
+   /* End implementation */
+   assign X = AA ^ BB;
 endmodule
\ No newline at end of file

From b3a91d6508943c8e5656af0a624e6ad115aec9c3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 11 Aug 2019 08:37:56 +0200
Subject: [PATCH 026/111] cleanup

---
 techlibs/efinix/arith_map.v | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v
index ef903171f..56e1b039f 100644
--- a/techlibs/efinix/arith_map.v
+++ b/techlibs/efinix/arith_map.v
@@ -32,6 +32,9 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
 
 	input CI, BI;
 	output [Y_WIDTH-1:0] CO;
+   
+   wire CIx;
+   wire [Y_WIDTH-1:0] COx;
 
 	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
 
@@ -41,14 +44,14 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
 
 	wire [Y_WIDTH-1:0] AA = A_buf;
 	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
-	wire [Y_WIDTH:0] C;
+	wire [Y_WIDTH-1:0] C = { COx, CIx };
 
     EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
     adder_cin  (
         .I0(CI),
         .I1(1'b1),
         .CI(1'b0),
-        .CO(C[0])
+        .CO(CIx)
 	);
 
 	genvar i;
@@ -59,13 +62,13 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
 			.I1(BB[i]),
 			.CI(C[i]),
 			.O(Y[i]),
-			.CO(C[i+1])
+			.CO(COx[i])
 		);
 		EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))				
 		adder_cout  (
 			.I0(1'b0),
 			.I1(1'b0),
-			.CI(C[i+1]),
+			.CI(COx[i]),
 			.O(CO[i])
 		);
 	  end: slice	  

From 8c8100e0df51401870fba13fccf5240461f76051 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 11 Aug 2019 10:17:49 +0200
Subject: [PATCH 027/111] Adding new pass to fix carry chain

---
 techlibs/efinix/Makefile.inc       |   1 +
 techlibs/efinix/efinix_fixcarry.cc | 122 +++++++++++++++++++++++++++++
 techlibs/efinix/synth_efinix.cc    |   1 +
 3 files changed, 124 insertions(+)
 create mode 100644 techlibs/efinix/efinix_fixcarry.cc

diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc
index d0593baec..47dadccdd 100644
--- a/techlibs/efinix/Makefile.inc
+++ b/techlibs/efinix/Makefile.inc
@@ -2,6 +2,7 @@
 OBJS += techlibs/efinix/synth_efinix.o
 OBJS += techlibs/efinix/efinix_gbuf.o
 OBJS += techlibs/efinix/efinix_determine_init.o
+OBJS += techlibs/efinix/efinix_fixcarry.o
 
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc
new file mode 100644
index 000000000..b7cd995b8
--- /dev/null
+++ b/techlibs/efinix/efinix_fixcarry.cc
@@ -0,0 +1,122 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2019  Miodrag Milanovic <miodrag@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+	if (GetSize(sig) == 0)
+		return State::S0;
+	return sig[0];
+}
+
+static void fix_carry_chain(Module *module)
+{
+	SigMap sigmap(module);
+
+	pool<SigBit> ci_bits;
+	dict<SigBit, SigBit> mapping_bits;
+
+	for (auto cell : module->cells())
+	{
+		if (cell->type == "\\EFX_ADD") {
+			SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0"));
+			SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1"));
+			if (bit_i0 == State::S0 && bit_i1== State::S0) {
+				SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
+				SigBit bit_o = sigmap(cell->getPort("\\O"));
+				ci_bits.insert(bit_ci);				
+				mapping_bits[bit_ci] = bit_o;
+			}
+		}
+	}
+	
+	vector<Cell*> adders_to_fix_cells;
+	for (auto cell : module->cells())
+	{
+		if (cell->type == "\\EFX_ADD") {
+			SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
+			SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0"));
+			SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1"));			
+			SigBit canonical_bit = sigmap(bit_ci);
+			if (!ci_bits.count(canonical_bit))
+				continue;			
+			if (bit_i0 == State::S0 && bit_i1== State::S0) 
+				continue;
+
+			adders_to_fix_cells.push_back(cell);
+			log("Found %s cell named %s with invalid CI signal.\n", log_id(cell->type), log_id(cell));
+		}
+	}
+
+	for (auto cell : adders_to_fix_cells)
+	{
+		SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
+		SigBit canonical_bit = sigmap(bit_ci);
+		auto bit = mapping_bits.at(canonical_bit);
+		log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
+		Cell *c = module->addCell(NEW_ID, "\\EFX_ADD");
+		SigBit new_bit = module->addWire(NEW_ID);
+		c->setParam("\\I0_POLARITY", State::S1);
+		c->setParam("\\I1_POLARITY", State::S1);
+		c->setPort("\\I0", bit);
+		c->setPort("\\I1", State::S1);
+		c->setPort("\\CI", State::S0);
+		c->setPort("\\CO", new_bit);
+		
+		cell->setPort("\\CI", new_bit);
+	}
+}
+
+struct EfinixCarryFixPass : public Pass {
+	EfinixCarryFixPass() : Pass("efinix_fixcarry", "Efinix: fix carry chain") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    efinix_fixcarry [options] [selection]\n");
+		log("\n");
+		log("Add Efinix adders to fix carry chain if needed.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing efinix_fixcarry pass (fix invalid carry chain).\n");
+		
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		Module *module = design->top_module();
+
+		if (module == nullptr)
+			log_cmd_error("No top module found.\n");
+
+		fix_carry_chain(module);		
+	}
+} EfinixCarryFixPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index 000a17310..d64491ca8 100644
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -191,6 +191,7 @@ struct SynthEfinixPass : public ScriptPass
 		if (check_label("map_gbuf"))
 		{
 			run("efinix_gbuf");
+			run("efinix_fixcarry");
 			run("clean");
 		}
 		

From e609537e386535047f045bf0b8df7ebc5f23c469 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 11 Aug 2019 10:46:48 +0200
Subject: [PATCH 028/111] Fixed data width

---
 techlibs/efinix/brams_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v
index 9ef01d026..3236f39a5 100644
--- a/techlibs/efinix/brams_map.v
+++ b/techlibs/efinix/brams_map.v
@@ -22,8 +22,8 @@ module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST";
 
 	EFX_RAM_5K #(
-   		.READ_WIDTH(20),
-   		.WRITE_WIDTH(20),
+   		.READ_WIDTH(CFG_DBITS),
+   		.WRITE_WIDTH(CFG_DBITS),
    		.OUTPUT_REG(1'b0),
    		.RCLK_POLARITY(1'b1),
    		.RE_POLARITY(1'b1),

From 853c755a0ca67ae0a75b5cf7783e395d9f49f389 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 11 Aug 2019 11:01:46 +0200
Subject: [PATCH 029/111] Replaced custom step with setundef

---
 techlibs/efinix/Makefile.inc             |  1 -
 techlibs/efinix/efinix_determine_init.cc | 89 ------------------------
 techlibs/efinix/synth_efinix.cc          |  2 +-
 3 files changed, 1 insertion(+), 91 deletions(-)
 delete mode 100644 techlibs/efinix/efinix_determine_init.cc

diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc
index 47dadccdd..f1ce58276 100644
--- a/techlibs/efinix/Makefile.inc
+++ b/techlibs/efinix/Makefile.inc
@@ -1,7 +1,6 @@
 
 OBJS += techlibs/efinix/synth_efinix.o
 OBJS += techlibs/efinix/efinix_gbuf.o
-OBJS += techlibs/efinix/efinix_determine_init.o
 OBJS += techlibs/efinix/efinix_fixcarry.o
 
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
diff --git a/techlibs/efinix/efinix_determine_init.cc b/techlibs/efinix/efinix_determine_init.cc
deleted file mode 100644
index 54da703ff..000000000
--- a/techlibs/efinix/efinix_determine_init.cc
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-struct EfinixDetermineInitPass : public Pass {
-	EfinixDetermineInitPass() : Pass("efinix_determine_init", "Efinix: Determine the init value of cells") { }
-	void help() YS_OVERRIDE
-	{
-		log("\n");
-		log("    efinix_determine_init [selection]\n");
-		log("\n");
-		log("Determine the init value of cells that doesn't allow unknown init value.\n");
-		log("\n");
-	}
-
-	Const determine_init(Const init)
-	{
-		for (int i = 0; i < GetSize(init); i++) {
-			if (init[i] != State::S0 && init[i] != State::S1)
-				init[i] = State::S0;
-		}
-
-		return init;
-	}
-
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-	{
-		log_header(design, "Executing EFINIX_DETERMINE_INIT pass (determine init value for cells).\n");
-
-		extra_args(args, args.size(), design);
-
-		int cnt = 0;
-		for (auto module : design->selected_modules())
-		{
-			for (auto cell : module->selected_cells())
-			{
-				if (cell->type == "\\EFX_RAM_5K")
-				{
-					cell->setParam("\\INIT_0", determine_init(cell->getParam("\\INIT_0")));					
-					cell->setParam("\\INIT_1", determine_init(cell->getParam("\\INIT_1")));
-					cell->setParam("\\INIT_2", determine_init(cell->getParam("\\INIT_2")));
-					cell->setParam("\\INIT_3", determine_init(cell->getParam("\\INIT_3")));
-					cell->setParam("\\INIT_4", determine_init(cell->getParam("\\INIT_4")));
-					cell->setParam("\\INIT_5", determine_init(cell->getParam("\\INIT_5")));
-					cell->setParam("\\INIT_6", determine_init(cell->getParam("\\INIT_6")));
-					cell->setParam("\\INIT_7", determine_init(cell->getParam("\\INIT_7")));
-					cell->setParam("\\INIT_8", determine_init(cell->getParam("\\INIT_8")));
-					cell->setParam("\\INIT_9", determine_init(cell->getParam("\\INIT_9")));
-					cell->setParam("\\INIT_A", determine_init(cell->getParam("\\INIT_A")));
-					cell->setParam("\\INIT_B", determine_init(cell->getParam("\\INIT_B")));
-					cell->setParam("\\INIT_C", determine_init(cell->getParam("\\INIT_C")));
-					cell->setParam("\\INIT_D", determine_init(cell->getParam("\\INIT_D")));
-					cell->setParam("\\INIT_E", determine_init(cell->getParam("\\INIT_E")));
-					cell->setParam("\\INIT_F", determine_init(cell->getParam("\\INIT_F")));
-					cell->setParam("\\INIT_10", determine_init(cell->getParam("\\INIT_10")));
-					cell->setParam("\\INIT_11", determine_init(cell->getParam("\\INIT_11")));
-					cell->setParam("\\INIT_12", determine_init(cell->getParam("\\INIT_12")));
-					cell->setParam("\\INIT_13", determine_init(cell->getParam("\\INIT_13")));
-
-					cnt++;
-				}
-			}
-		}
-		log_header(design, "Updated %d cells with determined init value.\n", cnt);
-	}
-} EfinixDetermineInitPass;
-
-PRIVATE_NAMESPACE_END
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index d64491ca8..26a8d4eda 100644
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -154,7 +154,7 @@ struct SynthEfinixPass : public ScriptPass
 		{
 			run("memory_bram -rules +/efinix/bram.txt");
 			run("techmap -map +/efinix/brams_map.v");
-			run("efinix_determine_init");
+			run("setundef -zero -params t:EFX_RAM_5K");
 		}
 
 		if (check_label("fine"))

From aa0c37722a99a308e64ea9581111adea2d97e46d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 11 Aug 2019 11:40:15 +0200
Subject: [PATCH 030/111] fix mixing signals on FF mapping

---
 techlibs/efinix/cells_map.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v
index 70c19635e..0aeab1902 100644
--- a/techlibs/efinix/cells_map.v
+++ b/techlibs/efinix/cells_map.v
@@ -8,14 +8,14 @@ module  \$_DFFE_PN_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE
 module  \$_DFFE_PP_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
 
 module  \$_DFF_NN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
-module  \$_DFF_NN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
 module  \$_DFF_PN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
 
 module  \$_DFF_NP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
-module  \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
 module  \$_DFF_PP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
-module  \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
 
 `ifndef NO_LUT
 module \$lut (A, Y);

From ead2b52b5a123e2c93578555de394a7a406e1fa5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 11 Aug 2019 13:59:39 +0200
Subject: [PATCH 031/111] one bit enable signal

---
 techlibs/efinix/brams_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v
index 3236f39a5..6786ae769 100644
--- a/techlibs/efinix/brams_map.v
+++ b/techlibs/efinix/brams_map.v
@@ -1,7 +1,7 @@
 module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	parameter CFG_ABITS = 8;
 	parameter CFG_DBITS = 20;
-	parameter CFG_ENABLE_A = 2;
+	parameter CFG_ENABLE_A = 1;
 
 	parameter CLKPOL2 = 1;
 	parameter CLKPOL3 = 1;

From 2897fe4d09118e37934b7e76f4990cc1d69a0cb5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 11 Aug 2019 17:05:24 +0200
Subject: [PATCH 032/111] Fix formating

---
 techlibs/efinix/arith_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v
index 56e1b039f..178f57bc5 100644
--- a/techlibs/efinix/arith_map.v
+++ b/techlibs/efinix/arith_map.v
@@ -33,8 +33,8 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
 	input CI, BI;
 	output [Y_WIDTH-1:0] CO;
    
-   wire CIx;
-   wire [Y_WIDTH-1:0] COx;
+    wire CIx;
+    wire [Y_WIDTH-1:0] COx;
 
 	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
 

From 5f561bdcb1d562d6f975b4a27beca1b8b7af908f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 12 Aug 2019 20:19:54 +0200
Subject: [PATCH 033/111] Proper arith for Anlogic and use standard pass

---
 techlibs/anlogic/Makefile.inc              |   2 +-
 techlibs/anlogic/anlogic_determine_init.cc |  72 ------------
 techlibs/anlogic/anlogic_fixcarry.cc       | 130 +++++++++++++++++++++
 techlibs/anlogic/arith_map.v               |  42 ++++---
 techlibs/anlogic/synth_anlogic.cc          |   7 +-
 5 files changed, 162 insertions(+), 91 deletions(-)
 delete mode 100644 techlibs/anlogic/anlogic_determine_init.cc
 create mode 100644 techlibs/anlogic/anlogic_fixcarry.cc

diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
index 67cf9cf10..9426b5ca5 100644
--- a/techlibs/anlogic/Makefile.inc
+++ b/techlibs/anlogic/Makefile.inc
@@ -1,7 +1,7 @@
 
 OBJS += techlibs/anlogic/synth_anlogic.o
 OBJS += techlibs/anlogic/anlogic_eqn.o
-OBJS += techlibs/anlogic/anlogic_determine_init.o
+OBJS += techlibs/anlogic/anlogic_fixcarry.o
 
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc
deleted file mode 100644
index c4089dac2..000000000
--- a/techlibs/anlogic/anlogic_determine_init.cc
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-struct AnlogicDetermineInitPass : public Pass {
-	AnlogicDetermineInitPass() : Pass("anlogic_determine_init", "Anlogic: Determine the init value of cells") { }
-	void help() YS_OVERRIDE
-	{
-		log("\n");
-		log("    anlogic_determine_init [selection]\n");
-		log("\n");
-		log("Determine the init value of cells that doesn't allow unknown init value.\n");
-		log("\n");
-	}
-
-	Const determine_init(Const init)
-	{
-		for (int i = 0; i < GetSize(init); i++) {
-			if (init[i] != State::S0 && init[i] != State::S1)
-				init[i] = State::S0;
-		}
-
-		return init;
-	}
-
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-	{
-		log_header(design, "Executing ANLOGIC_DETERMINE_INIT pass (determine init value for cells).\n");
-
-		extra_args(args, args.size(), design);
-
-		int cnt = 0;
-		for (auto module : design->selected_modules())
-		{
-			for (auto cell : module->selected_cells())
-			{
-				if (cell->type == "\\EG_LOGIC_DRAM16X4")
-				{
-					cell->setParam("\\INIT_D0", determine_init(cell->getParam("\\INIT_D0")));
-					cell->setParam("\\INIT_D1", determine_init(cell->getParam("\\INIT_D1")));
-					cell->setParam("\\INIT_D2", determine_init(cell->getParam("\\INIT_D2")));
-					cell->setParam("\\INIT_D3", determine_init(cell->getParam("\\INIT_D3")));
-					cnt++;
-				}
-			}
-		}
-		log_header(design, "Updated %d cells with determined init value.\n", cnt);
-	}
-} AnlogicDetermineInitPass;
-
-PRIVATE_NAMESPACE_END
diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc
new file mode 100644
index 000000000..87164d375
--- /dev/null
+++ b/techlibs/anlogic/anlogic_fixcarry.cc
@@ -0,0 +1,130 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2019  Miodrag Milanovic <miodrag@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+	if (GetSize(sig) == 0)
+		return State::S0;
+	return sig[0];
+}
+
+static void fix_carry_chain(Module *module)
+{
+	SigMap sigmap(module);
+
+	pool<SigBit> ci_bits;
+	dict<SigBit, SigBit> mapping_bits;
+
+	for (auto cell : module->cells())
+	{
+		if (cell->type == "\\AL_MAP_ADDER") {
+			if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
+			SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
+			SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));
+			if (bit_i0 == State::S0 && bit_i1== State::S0) {
+				SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
+				SigSpec o = cell->getPort("\\o");
+				if (GetSize(o) == 2) {
+					SigBit bit_o = o[0];
+					ci_bits.insert(bit_ci);				
+					mapping_bits[bit_ci] = bit_o;				
+				}
+			}
+		}
+	}
+	vector<Cell*> adders_to_fix_cells;
+	for (auto cell : module->cells())
+	{
+		if (cell->type == "\\AL_MAP_ADDER") {
+			if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
+			SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
+			SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
+			SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));			
+			SigBit canonical_bit = sigmap(bit_ci);
+			if (!ci_bits.count(canonical_bit))
+				continue;			
+			if (bit_i0 == State::S0 && bit_i1== State::S0) 
+				continue;
+
+			adders_to_fix_cells.push_back(cell);
+			log("Found %s cell named %s with invalid 'c' signal.\n", log_id(cell->type), log_id(cell));
+		}
+	}
+
+	for (auto cell : adders_to_fix_cells)
+	{
+		SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
+		SigBit canonical_bit = sigmap(bit_ci);
+		auto bit = mapping_bits.at(canonical_bit);
+		log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
+		Cell *c = module->addCell(NEW_ID, "\\AL_MAP_ADDER");
+		SigBit new_bit = module->addWire(NEW_ID);
+		SigBit dummy_bit = module->addWire(NEW_ID);
+		SigSpec bits;
+		bits.append(dummy_bit);
+		bits.append(new_bit);
+		c->setParam("\\ALUTYPE", Const("ADD_CARRY"));
+		c->setPort("\\a", bit);
+		c->setPort("\\b", State::S0);
+		c->setPort("\\c", State::S0);
+		c->setPort("\\o", bits);
+		
+		cell->setPort("\\c", new_bit);
+	}
+	
+}
+
+struct AnlogicCarryFixPass : public Pass {
+	AnlogicCarryFixPass() : Pass("anlogic_fixcarry", "Anlogic: fix carry chain") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    anlogic_fixcarry [options] [selection]\n");
+		log("\n");
+		log("Add Anlogic adders to fix carry chain if needed.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n");
+		
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		Module *module = design->top_module();
+
+		if (module == nullptr)
+			log_cmd_error("No top module found.\n");
+
+		fix_carry_chain(module);		
+	}
+} AnlogicCarryFixPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v
index 6d6a7ca37..d783b0212 100644
--- a/techlibs/anlogic/arith_map.v
+++ b/techlibs/anlogic/arith_map.v
@@ -31,7 +31,10 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
 	output [Y_WIDTH-1:0] X, Y;
 
 	input CI, BI;
-	output CO;
+	output [Y_WIDTH-1:0] CO;
+   
+	wire CIx;
+	wire [Y_WIDTH-1:0] COx;
 
 	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
 
@@ -41,15 +44,16 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
 
 	wire [Y_WIDTH-1:0] AA = A_buf;
 	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
-	wire [Y_WIDTH+1:0] COx;
-	wire [Y_WIDTH+2:0] C = {COx, CI};
+	wire [Y_WIDTH-1:0] C = { COx, CIx };
 
     wire dummy;
     AL_MAP_ADDER #(
     	.ALUTYPE("ADD_CARRY"))
     adder_cin  (
-        .a(C[0]),
-        .o({COx[0], dummy})
+        .a(CI),
+		.b(1'b0),
+		.c(1'b0),
+        .o({CIx, dummy})
 	);
 
 	genvar i;
@@ -59,18 +63,22 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
         ) adder_i (
             .a(AA[i]),
             .b(BB[i]),
-            .c(C[i+1]),
-            .o({COx[i+1],Y[i]})
+            .c(C[i]),
+            .o({COx[i],Y[i]})
         );
-	  end: slice
+
+		wire cout;
+		AL_MAP_ADDER #(
+			.ALUTYPE("ADD"))
+		adder_cout  (
+			.a(1'b0),
+			.b(1'b0),
+			.c(COx[i]),
+			.o({cout, CO[i]})
+		);
+	  end: slice	  
 	endgenerate
-	/* End implementation */
-	AL_MAP_ADDER #(
-		.ALUTYPE("ADD"))
-	adder_cout  (
-		.c(C[Y_WIDTH+1]),
-		.o(COx[Y_WIDTH+1])
-	);				
-	assign CO = COx[Y_WIDTH+1];
-	assign X = AA ^ BB;
+
+   /* End implementation */
+   assign X = AA ^ BB;
 endmodule
\ No newline at end of file
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 620bf3965..b87fc8566 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -154,7 +154,7 @@ struct SynthAnlogicPass : public ScriptPass
 		{
 			run("memory_bram -rules +/anlogic/drams.txt");
 			run("techmap -map +/anlogic/drams_map.v");
-			run("anlogic_determine_init");
+			run("setundef -zero -params t:EG_LOGIC_DRAM16X4");
 		}
 
 		if (check_label("fine"))
@@ -186,6 +186,11 @@ struct SynthAnlogicPass : public ScriptPass
 		{
 			run("techmap -map +/anlogic/cells_map.v");
 			run("clean");
+		}
+		
+		if (check_label("map_anlogic"))
+		{
+			run("anlogic_fixcarry");
 			run("anlogic_eqn");
 		}
 

From f4c62f33ac56bc5725c44ad822e75d2387f98061 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Mon, 12 Aug 2019 15:57:43 +0000
Subject: [PATCH 034/111] Add clock buffer insertion pass, improve iopadmap.

A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
---
 examples/mimas2/run_yosys.ys    |   3 +-
 passes/techmap/Makefile.inc     |   1 +
 passes/techmap/clkbufmap.cc     | 299 ++++++++++++++++++++++++++++++++
 passes/techmap/iopadmap.cc      |  76 +++++---
 techlibs/xilinx/cells_sim.v     |  16 ++
 techlibs/xilinx/cells_xtra.sh   | 144 +++++++--------
 techlibs/xilinx/cells_xtra.v    |  90 +++++++++-
 techlibs/xilinx/synth_xilinx.cc |  37 +++-
 techlibs/xilinx/xc6s_brams_bb.v |   2 +
 techlibs/xilinx/xc7_brams_bb.v  |   2 +
 10 files changed, 577 insertions(+), 93 deletions(-)
 create mode 100644 passes/techmap/clkbufmap.cc

diff --git a/examples/mimas2/run_yosys.ys b/examples/mimas2/run_yosys.ys
index b3204b1ca..b48877811 100644
--- a/examples/mimas2/run_yosys.ys
+++ b/examples/mimas2/run_yosys.ys
@@ -1,4 +1,3 @@
 read_verilog example.v
-synth_xilinx -top example -family xc6s
-iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I
+synth_xilinx -top example -family xc6s -ise
 write_edif -pvector bra example.edif
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 56f05eca4..631a80aa5 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -16,6 +16,7 @@ endif
 
 ifneq ($(SMALL),1)
 OBJS += passes/techmap/iopadmap.o
+OBJS += passes/techmap/clkbufmap.o
 OBJS += passes/techmap/hilomap.o
 OBJS += passes/techmap/extract.o
 OBJS += passes/techmap/extract_fa.o
diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc
new file mode 100644
index 000000000..9ecc83071
--- /dev/null
+++ b/passes/techmap/clkbufmap.cc
@@ -0,0 +1,299 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void split_portname_pair(std::string &port1, std::string &port2)
+{
+	size_t pos = port1.find_first_of(':');
+	if (pos != std::string::npos) {
+		port2 = port1.substr(pos+1);
+		port1 = port1.substr(0, pos);
+	}
+}
+
+std::vector<std::string> split(std::string text, const char *delim)
+{
+	std::vector<std::string> list;
+	char *p = strdup(text.c_str());
+	char *t = strtok(p, delim);
+	while (t != NULL) {
+		list.push_back(t);
+		t = strtok(NULL, delim);
+	}
+	free(p);
+	return list;
+}
+
+struct ClkbufmapPass : public Pass {
+	ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { }
+	void help() YS_OVERRIDE
+	{
+		log("\n");
+		log("    clkbufmap [options] [selection]\n");
+		log("\n");
+		log("Inserts global buffers between nets connected to clock inputs and their\n");
+		log("drivers.\n");
+		log("\n");
+		log("    -buf <celltype> <portname_out>:<portname_in>\n");
+		log("        Specifies the cell type to use for the global buffers\n");
+		log("        and its port names.  The first port will be connected to\n");
+		log("        the clock network sinks, and the second will be connected\n");
+		log("        to the actual clock source.  This option is required.\n");
+		log("\n");
+		log("    -inpad <celltype> <portname_out>:<portname_in>\n");
+		log("        If specified, a PAD cell of the given type is inserted on\n");
+		log("        clock nets that are also top module's inputs (in addition\n");
+		log("        to the global buffer).\n");
+		log("\n");
+	}
+
+	void module_queue(Design *design, Module *module, std::vector<Module *> &modules_sorted, pool<Module *> &modules_processed) {
+		if (modules_processed.count(module))
+			return;
+		for (auto cell : module->cells()) {
+			Module *submodule = design->module(cell->type);
+			if (!submodule)
+				continue;
+			module_queue(design, submodule, modules_sorted, modules_processed);
+		}
+		modules_sorted.push_back(module);
+		modules_processed.insert(module);
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing CLKBUFMAP pass (inserting global clock buffers).\n");
+
+		std::string buf_celltype, buf_portname, buf_portname2;
+		std::string inpad_celltype, inpad_portname, inpad_portname2;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			std::string arg = args[argidx];
+			if (arg == "-buf" && argidx+2 < args.size()) {
+				buf_celltype = args[++argidx];
+				buf_portname = args[++argidx];
+				split_portname_pair(buf_portname, buf_portname2);
+				continue;
+			}
+			if (arg == "-inpad" && argidx+2 < args.size()) {
+				inpad_celltype = args[++argidx];
+				inpad_portname = args[++argidx];
+				split_portname_pair(inpad_portname, inpad_portname2);
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (buf_celltype.empty())
+			log_error("The -buf option is required.");
+
+		// Cell type, port name, bit index.
+		pool<pair<IdString, pair<IdString, int>>> sink_ports;
+		pool<pair<IdString, pair<IdString, int>>> buf_ports;
+
+		// Process submodules before module using them.
+		std::vector<Module *> modules_sorted;
+		pool<Module *> modules_processed;
+		for (auto module : design->selected_modules())
+			module_queue(design, module, modules_sorted, modules_processed);
+
+		for (auto module : modules_sorted)
+		{
+			if (module->get_blackbox_attribute()) {
+				auto it = module->attributes.find("\\clkbuf_driver");
+				if (it != module->attributes.end()) {
+					auto value = it->second.decode_string();
+					for (auto name : split(value, ",")) {
+						auto wire = module->wire(RTLIL::escape_id(name));
+						if (!wire)
+							log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
+						for (int i = 0; i < GetSize(wire); i++)
+							buf_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i)));
+					}
+				}
+				it = module->attributes.find("\\clkbuf_sink");
+				if (it != module->attributes.end()) {
+					auto value = it->second.decode_string();
+					for (auto name : split(value, ",")) {
+						auto wire = module->wire(RTLIL::escape_id(name));
+						if (!wire)
+							log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
+						for (int i = 0; i < GetSize(wire); i++)
+							sink_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i)));
+					}
+				}
+				continue;
+			}
+			pool<SigBit> sink_wire_bits;
+			pool<SigBit> buf_wire_bits;
+			pool<SigBit> driven_wire_bits;
+			SigMap sigmap(module);
+			// bit -> (buffer, buffer's input)
+			dict<SigBit, pair<Cell *, Wire *>> buffered_bits;
+
+			// First, collect nets that could use a clock buffer.
+			for (auto cell : module->cells())
+			for (auto port : cell->connections())
+			for (int i = 0; i < port.second.size(); i++)
+				if (sink_ports.count(make_pair(cell->type, make_pair(port.first, i))))
+					sink_wire_bits.insert(sigmap(port.second[i]));
+
+			// Second, collect ones that already have a clock buffer.
+			for (auto cell : module->cells())
+			for (auto port : cell->connections())
+			for (int i = 0; i < port.second.size(); i++)
+				if (buf_ports.count(make_pair(cell->type, make_pair(port.first, i))))
+					buf_wire_bits.insert(sigmap(port.second[i]));
+
+			// Collect all driven bits.
+			for (auto cell : module->cells())
+			for (auto port : cell->connections())
+				if (cell->output(port.first))
+					for (int i = 0; i < port.second.size(); i++)
+						driven_wire_bits.insert(port.second[i]);
+
+			// Insert buffers.
+			std::vector<pair<Wire *, Wire *>> input_queue;
+			for (auto wire : module->selected_wires())
+			{
+				// Should not happen.
+				if (wire->port_input && wire->port_output)
+					continue;
+				if (wire->get_bool_attribute("\\clkbuf_inhibit"))
+					continue;
+
+				pool<int> input_bits;
+
+				for (int i = 0; i < GetSize(wire); i++)
+				{
+					SigBit wire_bit(wire, i);
+					SigBit mapped_wire_bit = sigmap(wire_bit);
+					if (buf_wire_bits.count(mapped_wire_bit)) {
+						// Already buffered downstream.  If this is an output, mark it.
+						if (wire->port_output)
+							buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
+					} else if (!sink_wire_bits.count(mapped_wire_bit)) {
+						// Nothing to do.
+					} else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute("\\top"))) {
+						// Clock network not yet buffered, driven by one of
+						// our cells or a top-level input -- buffer it.
+
+						log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i);
+						RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
+						Wire *iwire = module->addWire(NEW_ID);
+						cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
+						cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
+						if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute("\\top")) {
+							log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i);
+							RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
+							cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
+							iwire = module->addWire(NEW_ID);
+							cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
+						}
+						buffered_bits[mapped_wire_bit] = make_pair(cell, iwire);
+
+						if (wire->port_input) {
+							input_bits.insert(i);
+						}
+					} else if (wire->port_input) {
+						// A clock input in a submodule -- mark it, let higher level
+						// worry about it.
+						if (wire->port_input)
+							sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
+					}
+				}
+				if (!input_bits.empty()) {
+					// This is an input port and some buffers were inserted -- we need
+					// to create a new input wire and transfer attributes.
+					Wire *new_wire = module->addWire(NEW_ID, wire);
+
+					for (int i = 0; i < wire->width; i++) {
+						SigBit wire_bit(wire, i);
+						SigBit mapped_wire_bit = sigmap(wire_bit);
+						auto it = buffered_bits.find(mapped_wire_bit);
+						if (it != buffered_bits.end()) {
+
+							module->connect(it->second.second, SigSpec(new_wire, i));
+						} else {
+							module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
+						}
+					}
+					input_queue.push_back(make_pair(wire, new_wire));
+				}
+			}
+
+			// Mark any newly-buffered output ports as such.
+			for (auto wire : module->selected_wires()) {
+				if (wire->port_input || !wire->port_output)
+					continue;
+				for (int i = 0; i < GetSize(wire); i++)
+				{
+					SigBit wire_bit(wire, i);
+					SigBit mapped_wire_bit = sigmap(wire_bit);
+					if (buffered_bits.count(mapped_wire_bit))
+						buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
+				}
+			}
+
+			// Reconnect the drivers to buffer inputs.
+			for (auto cell : module->cells())
+			for (auto port : cell->connections()) {
+				if (!cell->output(port.first))
+					continue;
+				SigSpec sig = port.second;
+				bool newsig = false;
+				for (auto &bit : sig) {
+					const auto it = buffered_bits.find(sigmap(bit));
+					if (it == buffered_bits.end())
+						continue;
+					// Avoid substituting buffer's own output pin.
+					if (cell == it->second.first)
+						continue;
+					bit = it->second.second;
+					newsig = true;
+				}
+				if (newsig)
+					cell->setPort(port.first, sig);
+			}
+
+			// This has to be done last, to avoid upsetting sigmap before the port reconnections.
+			for (auto &it : input_queue) {
+				Wire *wire = it.first;
+				Wire *new_wire = it.second;
+				module->swap_names(new_wire, wire);
+				wire->attributes.clear();
+				wire->port_id = 0;
+				wire->port_input = false;
+				wire->port_output = false;
+			}
+
+			module->fixup_ports();
+		}
+	}
+} ClkbufmapPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index efcc082d5..e3d68ab0c 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -32,6 +32,19 @@ void split_portname_pair(std::string &port1, std::string &port2)
 	}
 }
 
+std::vector<std::string> split(std::string text, const char *delim)
+{
+	std::vector<std::string> list;
+	char *p = strdup(text.c_str());
+	char *t = strtok(p, delim);
+	while (t != NULL) {
+		list.push_back(t);
+		t = strtok(NULL, delim);
+	}
+	free(p);
+	return list;
+}
+
 struct IopadmapPass : public Pass {
 	IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
 	void help() YS_OVERRIDE
@@ -64,6 +77,11 @@ struct IopadmapPass : public Pass {
 		log("        of the tristate driver and the 2nd portname is the internal output\n");
 		log("        buffering the external signal.\n");
 		log("\n");
+		log("    -ignore <celltype> <portname>[:<portname>]*\n");
+		log("        Skips mapping inputs/outputs that are already connected to given\n");
+		log("        ports of the given cell.  Can be used multiple times.  This is in\n");
+		log("        addition to the cells specified as mapping targets.\n");
+		log("\n");
 		log("    -widthparam <param_name>\n");
 		log("        Use the specified parameter name to set the port width.\n");
 		log("\n");
@@ -88,6 +106,7 @@ struct IopadmapPass : public Pass {
 		std::string toutpad_celltype, toutpad_portname, toutpad_portname2, toutpad_portname3;
 		std::string tinoutpad_celltype, tinoutpad_portname, tinoutpad_portname2, tinoutpad_portname3, tinoutpad_portname4;
 		std::string widthparam, nameparam;
+		pool<pair<IdString, IdString>> ignore;
 		bool flag_bits = false;
 
 		size_t argidx;
@@ -127,6 +146,18 @@ struct IopadmapPass : public Pass {
 				split_portname_pair(tinoutpad_portname3, tinoutpad_portname4);
 				continue;
 			}
+			if (arg == "-ignore" && argidx+2 < args.size()) {
+				std::string ignore_celltype = args[++argidx];
+				std::string ignore_portname = args[++argidx];
+				std::string ignore_portname2;
+				while (!ignore_portname.empty()) {
+					split_portname_pair(ignore_portname, ignore_portname2);
+					ignore.insert(make_pair(RTLIL::escape_id(ignore_celltype), RTLIL::escape_id(ignore_portname)));
+
+					ignore_portname = ignore_portname2;
+				}
+				continue;
+			}
 			if (arg == "-widthparam" && argidx+1 < args.size()) {
 				widthparam = args[++argidx];
 				continue;
@@ -143,6 +174,28 @@ struct IopadmapPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		if (!inpad_portname2.empty())
+			ignore.insert(make_pair(RTLIL::escape_id(inpad_celltype), RTLIL::escape_id(inpad_portname2)));
+		if (!outpad_portname2.empty())
+			ignore.insert(make_pair(RTLIL::escape_id(outpad_celltype), RTLIL::escape_id(outpad_portname2)));
+		if (!inoutpad_portname2.empty())
+			ignore.insert(make_pair(RTLIL::escape_id(inoutpad_celltype), RTLIL::escape_id(inoutpad_portname2)));
+		if (!toutpad_portname3.empty())
+			ignore.insert(make_pair(RTLIL::escape_id(toutpad_celltype), RTLIL::escape_id(toutpad_portname3)));
+		if (!tinoutpad_portname4.empty())
+			ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname4)));
+
+		for (auto module : design->modules())
+		{
+			auto it = module->attributes.find("\\iopad_external_pin");
+			if (it != module->attributes.end()) {
+				auto value = it->second.decode_string();
+				for (auto name : split(value, ",")) {
+					ignore.insert(make_pair(module->name, RTLIL::escape_id(name)));
+				}
+			}
+		}
+
 		for (auto module : design->selected_modules())
 		{
 			dict<IdString, pool<int>> skip_wires;
@@ -150,28 +203,11 @@ struct IopadmapPass : public Pass {
 			SigMap sigmap(module);
 
 			for (auto cell : module->cells())
-			{
-				if (cell->type == RTLIL::escape_id(inpad_celltype) && cell->hasPort(RTLIL::escape_id(inpad_portname2)))
-					for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inpad_portname2))))
+			for (auto port : cell->connections())
+				if (ignore.count(make_pair(cell->type, port.first)))
+					for (auto bit : sigmap(port.second))
 						skip_wire_bits.insert(bit);
 
-				if (cell->type == RTLIL::escape_id(outpad_celltype) && cell->hasPort(RTLIL::escape_id(outpad_portname2)))
-					for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(outpad_portname2))))
-						skip_wire_bits.insert(bit);
-
-				if (cell->type == RTLIL::escape_id(inoutpad_celltype) && cell->hasPort(RTLIL::escape_id(inoutpad_portname2)))
-					for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inoutpad_portname2))))
-						skip_wire_bits.insert(bit);
-
-				if (cell->type == RTLIL::escape_id(toutpad_celltype) && cell->hasPort(RTLIL::escape_id(toutpad_portname3)))
-					for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(toutpad_portname3))))
-						skip_wire_bits.insert(bit);
-
-				if (cell->type == RTLIL::escape_id(tinoutpad_celltype) && cell->hasPort(RTLIL::escape_id(tinoutpad_portname4)))
-					for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(tinoutpad_portname4))))
-						skip_wire_bits.insert(bit);
-			}
-
 			if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
 			{
 				dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 05e46b4e7..d5815ca77 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -42,10 +42,12 @@ module OBUF(output O, input I);
   assign O = I;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFG(output O, input I);
   assign O = I;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFGCTRL(
     output O,
     input I0, input I1,
@@ -72,6 +74,7 @@ assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
 
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFHCE(output O, input I, input CE);
 
 parameter [0:0] INIT_OUT = 1'b0;
@@ -213,6 +216,7 @@ endmodule
 
 `endif
 
+(* clkbuf_sink = "C" *)
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -225,6 +229,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   endcase endgenerate
 endmodule
 
+(* clkbuf_sink = "C" *)
 module FDSE (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -237,6 +242,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   endcase endgenerate
 endmodule
 
+(* clkbuf_sink = "C" *)
 module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -251,6 +257,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   endcase endgenerate
 endmodule
 
+(* clkbuf_sink = "C" *)
 module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -265,30 +272,35 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   endcase endgenerate
 endmodule
 
+(* clkbuf_sink = "C" *)
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
+(* clkbuf_sink = "C" *)
 module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
+(* clkbuf_sink = "C" *)
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
+(* clkbuf_sink = "C" *)
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 (* abc_box_id = 5, abc_scc_break="D,WE" *)
 module RAM32X1D (
   output DPO, SPO,
@@ -307,6 +319,7 @@ module RAM32X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 (* abc_box_id = 6, abc_scc_break="D,WE" *)
 module RAM64X1D (
   output DPO, SPO,
@@ -325,6 +338,7 @@ module RAM64X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 (* abc_box_id = 7, abc_scc_break="D,WE" *)
 module RAM128X1D (
   output       DPO, SPO,
@@ -340,6 +354,7 @@ module RAM128X1D (
   always @(posedge clk) if (WE) mem[A] <= D;
 endmodule
 
+(* clkbuf_sink = "CLK" *)
 module SRL16E (
   output Q,
   input A0, A1, A2, A3, CE, CLK, D
@@ -358,6 +373,7 @@ module SRL16E (
   endgenerate
 endmodule
 
+(* clkbuf_sink = "CLK" *)
 module SRLC32E (
   output Q,
   output Q31,
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index 53b528820..3291e46a8 100644
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -1,7 +1,12 @@
 #!/bin/bash
 
 set -e
-libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src"
+if [ -z "$1" ]
+then
+	libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src"
+else
+	libdir=$1
+fi
 
 function xtract_cell_decl()
 {
@@ -24,33 +29,33 @@ function xtract_cell_decl()
 	echo
 
 	# Design elements types listed in Xilinx UG953
-	xtract_cell_decl BSCANE2
-	# xtract_cell_decl BUFG
-	xtract_cell_decl BUFGCE
-	xtract_cell_decl BUFGCE_1
-	#xtract_cell_decl BUFGCTRL
-	xtract_cell_decl BUFGMUX
-	xtract_cell_decl BUFGMUX_1
-	xtract_cell_decl BUFGMUX_CTRL
-	xtract_cell_decl BUFH
-	#xtract_cell_decl BUFHCE
-	xtract_cell_decl BUFIO
-	xtract_cell_decl BUFMR
-	xtract_cell_decl BUFMRCE
-	xtract_cell_decl BUFR
+	xtract_cell_decl BSCANE2 "(* keep *)"
+	# xtract_cell_decl BUFG "(* clkbuf_driver = \"O\" *)"
+	xtract_cell_decl BUFGCE "(* clkbuf_driver = \"O\" *)"
+	xtract_cell_decl BUFGCE_1 "(* clkbuf_driver = \"O\" *)"
+	#xtract_cell_decl BUFGCTRL "(* clkbuf_driver = \"O\" *)"
+	xtract_cell_decl BUFGMUX "(* clkbuf_driver = \"O\" *)"
+	xtract_cell_decl BUFGMUX_1 "(* clkbuf_driver = \"O\" *)"
+	xtract_cell_decl BUFGMUX_CTRL "(* clkbuf_driver = \"O\" *)"
+	xtract_cell_decl BUFH "(* clkbuf_driver = \"O\" *)"
+	#xtract_cell_decl BUFHCE "(* clkbuf_driver = \"O\" *)"
+	xtract_cell_decl BUFIO "(* clkbuf_driver = \"O\" *)"
+	xtract_cell_decl BUFMR "(* clkbuf_driver = \"O\" *)"
+	xtract_cell_decl BUFMRCE "(* clkbuf_driver = \"O\" *)"
+	xtract_cell_decl BUFR "(* clkbuf_driver = \"O\" *)"
 	xtract_cell_decl CAPTUREE2 "(* keep *)"
 	# xtract_cell_decl CARRY4
-	xtract_cell_decl CFGLUT5
+	xtract_cell_decl CFGLUT5 "(* clkbuf_sink = \"CLK\" *)"
 	xtract_cell_decl DCIRESET "(* keep *)"
 	xtract_cell_decl DNA_PORT
-	xtract_cell_decl DSP48E1
+	xtract_cell_decl DSP48E1 "(* clkbuf_sink = \"CLK\" *)"
 	xtract_cell_decl EFUSE_USR
 	# xtract_cell_decl FDCE
 	# xtract_cell_decl FDPE
 	# xtract_cell_decl FDRE
 	# xtract_cell_decl FDSE
-	xtract_cell_decl FIFO18E1
-	xtract_cell_decl FIFO36E1
+	xtract_cell_decl FIFO18E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
+	xtract_cell_decl FIFO36E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
 	xtract_cell_decl FRAME_ECCE2
 	xtract_cell_decl GTHE2_CHANNEL
 	xtract_cell_decl GTHE2_COMMON
@@ -58,31 +63,34 @@ function xtract_cell_decl()
 	xtract_cell_decl GTPE2_COMMON
 	xtract_cell_decl GTXE2_CHANNEL
 	xtract_cell_decl GTXE2_COMMON
-	# xtract_cell_decl IBUF
-	xtract_cell_decl IBUF_IBUFDISABLE
-	xtract_cell_decl IBUF_INTERMDISABLE
-	xtract_cell_decl IBUFDS
-	xtract_cell_decl IBUFDS_DIFF_OUT
-	xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE
-	xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE
-	xtract_cell_decl IBUFDS_GTE2
-	xtract_cell_decl IBUFDS_IBUFDISABLE
-	xtract_cell_decl IBUFDS_INTERMDISABLE
+	# xtract_cell_decl IBUF "(* iopad_external_pin = \"I\" *)"
+	xtract_cell_decl IBUF_IBUFDISABLE "(* iopad_external_pin = \"I\" *)"
+	xtract_cell_decl IBUF_INTERMDISABLE "(* iopad_external_pin = \"I\" *)"
+	xtract_cell_decl IBUFDS "(* iopad_external_pin = \"I,IB\" *)"
+	xtract_cell_decl IBUFDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)"
+	xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)"
+	xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)"
+	xtract_cell_decl IBUFDS_GTE2 "(* iopad_external_pin = \"I,IB\" *)"
+	xtract_cell_decl IBUFDS_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)"
+	xtract_cell_decl IBUFDS_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)"
+	xtract_cell_decl IBUFG "(* iopad_external_pin = \"I\" *)"
+	xtract_cell_decl IBUFGDS "(* iopad_external_pin = \"I,IB\" *)"
+	xtract_cell_decl IBUFGDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)"
 	xtract_cell_decl ICAPE2 "(* keep *)"
-	xtract_cell_decl IDDR
-	xtract_cell_decl IDDR_2CLK
-	xtract_cell_decl IDELAYCTRL "(* keep *)"
-	xtract_cell_decl IDELAYE2
-	xtract_cell_decl IN_FIFO
-	xtract_cell_decl IOBUF
-	xtract_cell_decl IOBUF_DCIEN
-	xtract_cell_decl IOBUF_INTERMDISABLE
-	xtract_cell_decl IOBUFDS
-	xtract_cell_decl IOBUFDS_DCIEN
-	xtract_cell_decl IOBUFDS_DIFF_OUT
-	xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN
-	xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE
-	xtract_cell_decl ISERDESE2
+	xtract_cell_decl IDDR "(* clkbuf_sink = \"C\" *)"
+	xtract_cell_decl IDDR_2CLK "(* clkbuf_sink = \"C,CB\" *)"
+	xtract_cell_decl IDELAYCTRL "(* keep *) (* clkbuf_sink = \"REFCLK\" *)"
+	xtract_cell_decl IDELAYE2 "(* clkbuf_sink = \"C\" *)"
+	xtract_cell_decl IN_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
+	xtract_cell_decl IOBUF "(* iopad_external_pin = \"IO\" *)"
+	xtract_cell_decl IOBUF_DCIEN "(* iopad_external_pin = \"IO\" *)"
+	xtract_cell_decl IOBUF_INTERMDISABLE "(* iopad_external_pin = \"IO\" *)"
+	xtract_cell_decl IOBUFDS "(* iopad_external_pin = \"IO\" *)"
+	xtract_cell_decl IOBUFDS_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)"
+	xtract_cell_decl IOBUFDS_DIFF_OUT "(* iopad_external_pin = \"IO,IOB\" *)"
+	xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)"
+	xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"IO,IOB\" *)"
+	xtract_cell_decl ISERDESE2 "(* clkbuf_sink = \"CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB\" *)"
 	xtract_cell_decl KEEPER
 	xtract_cell_decl LDCE
 	xtract_cell_decl LDPE
@@ -97,14 +105,14 @@ function xtract_cell_decl()
 	xtract_cell_decl MMCME2_BASE
 	# xtract_cell_decl MUXF7
 	# xtract_cell_decl MUXF8
-	# xtract_cell_decl OBUF
-	xtract_cell_decl OBUFDS
-	xtract_cell_decl OBUFT
-	xtract_cell_decl OBUFTDS
-	xtract_cell_decl ODDR
-	xtract_cell_decl ODELAYE2
-	xtract_cell_decl OSERDESE2
-	xtract_cell_decl OUT_FIFO
+	# xtract_cell_decl OBUF "(* iopad_external_pin = \"O\" *)"
+	xtract_cell_decl OBUFDS "(* iopad_external_pin = \"O,OB\" *)"
+	xtract_cell_decl OBUFT "(* iopad_external_pin = \"O\" *)"
+	xtract_cell_decl OBUFTDS "(* iopad_external_pin = \"O,OB\" *)"
+	xtract_cell_decl ODDR "(* clkbuf_sink = \"C\" *)"
+	xtract_cell_decl ODELAYE2 "(* clkbuf_sink = \"C\" *)"
+	xtract_cell_decl OSERDESE2 "(* clkbuf_sink = \"CLK,CLKDIV\" *)"
+	xtract_cell_decl OUT_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
 	xtract_cell_decl PHASER_IN
 	xtract_cell_decl PHASER_IN_PHY
 	xtract_cell_decl PHASER_OUT
@@ -116,27 +124,27 @@ function xtract_cell_decl()
 	xtract_cell_decl PS7 "(* keep *)"
 	xtract_cell_decl PULLDOWN
 	xtract_cell_decl PULLUP
-	#xtract_cell_decl RAM128X1D
-	xtract_cell_decl RAM128X1S
-	xtract_cell_decl RAM256X1S
-	xtract_cell_decl RAM32M
-	#xtract_cell_decl RAM32X1D
-	xtract_cell_decl RAM32X1S
-	xtract_cell_decl RAM32X1S_1
-	xtract_cell_decl RAM32X2S
-	xtract_cell_decl RAM64M
-	#xtract_cell_decl RAM64X1D
-	xtract_cell_decl RAM64X1S
-	xtract_cell_decl RAM64X1S_1
-	xtract_cell_decl RAM64X2S
-	# xtract_cell_decl RAMB18E1
-	# xtract_cell_decl RAMB36E1
+	#xtract_cell_decl RAM128X1D "(* clkbuf_sink = \"WCLK\" *)"
+	xtract_cell_decl RAM128X1S "(* clkbuf_sink = \"WCLK\" *)"
+	xtract_cell_decl RAM256X1S "(* clkbuf_sink = \"WCLK\" *)"
+	xtract_cell_decl RAM32M "(* clkbuf_sink = \"WCLK\" *)"
+	#xtract_cell_decl RAM32X1D "(* clkbuf_sink = \"WCLK\" *)"
+	xtract_cell_decl RAM32X1S "(* clkbuf_sink = \"WCLK\" *)"
+	xtract_cell_decl RAM32X1S_1 "(* clkbuf_sink = \"WCLK\" *)"
+	xtract_cell_decl RAM32X2S "(* clkbuf_sink = \"WCLK\" *)"
+	xtract_cell_decl RAM64M "(* clkbuf_sink = \"WCLK\" *)"
+	#xtract_cell_decl RAM64X1D "(* clkbuf_sink = \"WCLK\" *)"
+	xtract_cell_decl RAM64X1S "(* clkbuf_sink = \"WCLK\" *)"
+	xtract_cell_decl RAM64X1S_1 "(* clkbuf_sink = \"WCLK\" *)"
+	xtract_cell_decl RAM64X2S "(* clkbuf_sink = \"WCLK\" *)"
+	# xtract_cell_decl RAMB18E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)"
+	# xtract_cell_decl RAMB36E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)"
 	xtract_cell_decl ROM128X1
 	xtract_cell_decl ROM256X1
 	xtract_cell_decl ROM32X1
 	xtract_cell_decl ROM64X1
-	#xtract_cell_decl SRL16E
-	#xtract_cell_decl SRLC32E
+	#xtract_cell_decl SRL16E "(* clkbuf_sink = \"CLK\" *)"
+	#xtract_cell_decl SRLC32E "(* clkbuf_sink = \"CLK\" *)"
 	xtract_cell_decl STARTUPE2 "(* keep *)"
 	xtract_cell_decl USR_ACCESSE2
 	xtract_cell_decl XADC
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 15fa1b63a..0fbbc0fdf 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -1,5 +1,6 @@
 // Created by cells_xtra.sh from Xilinx models
 
+(* keep *)
 module BSCANE2 (...);
     parameter DISABLE_JTAG = "FALSE";
     parameter integer JTAG_CHAIN = 1;
@@ -16,6 +17,7 @@ module BSCANE2 (...);
     input TDO;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFGCE (...);
     parameter CE_TYPE = "SYNC";
     parameter [0:0] IS_CE_INVERTED = 1'b0;
@@ -25,23 +27,28 @@ module BUFGCE (...);
     input I;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFGCE_1 (...);
     output O;
-    input CE, I;
+    input CE;
+    input I;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFGMUX (...);
     parameter CLK_SEL_TYPE = "SYNC";
     output O;
     input I0, I1, S;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFGMUX_1 (...);
     parameter CLK_SEL_TYPE = "SYNC";
     output O;
     input I0, I1, S;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFGMUX_CTRL (...);
     output O;
     input I0;
@@ -49,21 +56,25 @@ module BUFGMUX_CTRL (...);
     input S;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFH (...);
     output O;
     input I;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFIO (...);
     output O;
     input I;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFMR (...);
     output O;
     input I;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFMRCE (...);
     parameter CE_TYPE = "SYNC";
     parameter integer INIT_OUT = 0;
@@ -73,6 +84,7 @@ module BUFMRCE (...);
     input I;
 endmodule
 
+(* clkbuf_driver = "O" *)
 module BUFR (...);
     output O;
     input CE;
@@ -89,6 +101,7 @@ module CAPTUREE2 (...);
     input CLK;
 endmodule
 
+(* clkbuf_sink = "CLK" *)
 module CFGLUT5 (...);
     parameter [31:0] INIT = 32'h00000000;
     parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -111,6 +124,7 @@ module DNA_PORT (...);
     input CLK, DIN, READ, SHIFT;
 endmodule
 
+(* clkbuf_sink = "CLK" *)
 module DSP48E1 (...);
     parameter integer ACASCREG = 1;
     parameter integer ADREG = 1;
@@ -198,6 +212,7 @@ module EFUSE_USR (...);
     output [31:0] EFUSEUSR;
 endmodule
 
+(* clkbuf_sink = "RDCLK,WRCLK" *)
 module FIFO18E1 (...);
     parameter ALMOST_EMPTY_OFFSET = 13'h0080;
     parameter ALMOST_FULL_OFFSET = 13'h0080;
@@ -236,6 +251,7 @@ module FIFO18E1 (...);
     input WREN;
 endmodule
 
+(* clkbuf_sink = "RDCLK,WRCLK" *)
 module FIFO36E1 (...);
     parameter ALMOST_EMPTY_OFFSET = 13'h0080;
     parameter ALMOST_FULL_OFFSET = 13'h0080;
@@ -1963,6 +1979,7 @@ module GTXE2_COMMON (...);
     input [7:0] PMARSVD;
 endmodule
 
+(* iopad_external_pin = "I" *)
 module IBUF_IBUFDISABLE (...);
     parameter IBUF_LOW_PWR = "TRUE";
     parameter IOSTANDARD = "DEFAULT";
@@ -1973,6 +1990,7 @@ module IBUF_IBUFDISABLE (...);
     input IBUFDISABLE;
 endmodule
 
+(* iopad_external_pin = "I" *)
 module IBUF_INTERMDISABLE (...);
     parameter IBUF_LOW_PWR = "TRUE";
     parameter IOSTANDARD = "DEFAULT";
@@ -1984,6 +2002,7 @@ module IBUF_INTERMDISABLE (...);
     input INTERMDISABLE;
 endmodule
 
+(* iopad_external_pin = "I,IB" *)
 module IBUFDS (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter DIFF_TERM = "FALSE";
@@ -1996,6 +2015,7 @@ module IBUFDS (...);
     input I, IB;
 endmodule
 
+(* iopad_external_pin = "I,IB" *)
 module IBUFDS_DIFF_OUT (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2005,6 +2025,7 @@ module IBUFDS_DIFF_OUT (...);
     input I, IB;
 endmodule
 
+(* iopad_external_pin = "I,IB" *)
 module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2019,6 +2040,7 @@ module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
     input IBUFDISABLE;
 endmodule
 
+(* iopad_external_pin = "I,IB" *)
 module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2034,6 +2056,7 @@ module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
     input INTERMDISABLE;
 endmodule
 
+(* iopad_external_pin = "I,IB" *)
 module IBUFDS_GTE2 (...);
     parameter CLKCM_CFG = "TRUE";
     parameter CLKRCV_TRST = "TRUE";
@@ -2045,6 +2068,7 @@ module IBUFDS_GTE2 (...);
     input IB;
 endmodule
 
+(* iopad_external_pin = "I,IB" *)
 module IBUFDS_IBUFDISABLE (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2058,6 +2082,7 @@ module IBUFDS_IBUFDISABLE (...);
     input IBUFDISABLE;
 endmodule
 
+(* iopad_external_pin = "I,IB" *)
 module IBUFDS_INTERMDISABLE (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2072,6 +2097,37 @@ module IBUFDS_INTERMDISABLE (...);
     input INTERMDISABLE;
 endmodule
 
+(* iopad_external_pin = "I" *)
+module IBUFG (...);
+    parameter CAPACITANCE = "DONT_CARE";
+    parameter IBUF_DELAY_VALUE = "0";
+    parameter IBUF_LOW_PWR = "TRUE";
+    parameter IOSTANDARD = "DEFAULT";
+    output O;
+    input I;
+endmodule
+
+(* iopad_external_pin = "I,IB" *)
+module IBUFGDS (...);
+    parameter CAPACITANCE = "DONT_CARE";
+    parameter DIFF_TERM = "FALSE";
+    parameter IBUF_DELAY_VALUE = "0";
+    parameter IBUF_LOW_PWR = "TRUE";
+    parameter IOSTANDARD = "DEFAULT";
+    output O;
+    input I, IB;
+endmodule
+
+(* iopad_external_pin = "I,IB" *)
+module IBUFGDS_DIFF_OUT (...);
+    parameter DIFF_TERM = "FALSE";
+    parameter DQS_BIAS = "FALSE";
+    parameter IBUF_LOW_PWR = "TRUE";
+    parameter IOSTANDARD = "DEFAULT";
+    output O, OB;
+    input I, IB;
+endmodule
+
 (* keep *)
 module ICAPE2 (...);
     parameter [31:0] DEVICE_ID = 32'h04244093;
@@ -2084,6 +2140,7 @@ module ICAPE2 (...);
     input [31:0] I;
 endmodule
 
+(* clkbuf_sink = "C" *)
 module IDDR (...);
     parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
     parameter INIT_Q1 = 1'b0;
@@ -2102,6 +2159,7 @@ module IDDR (...);
     input S;
 endmodule
 
+(* clkbuf_sink = "C,CB" *)
 module IDDR_2CLK (...);
     parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
     parameter INIT_Q1 = 1'b0;
@@ -2120,7 +2178,7 @@ module IDDR_2CLK (...);
     input S;
 endmodule
 
-(* keep *)
+(* keep *) (* clkbuf_sink = "REFCLK" *)
 module IDELAYCTRL (...);
     parameter SIM_DEVICE = "7SERIES";
     output RDY;
@@ -2128,6 +2186,7 @@ module IDELAYCTRL (...);
     input RST;
 endmodule
 
+(* clkbuf_sink = "C" *)
 module IDELAYE2 (...);
     parameter CINVCTRL_SEL = "FALSE";
     parameter DELAY_SRC = "IDATAIN";
@@ -2155,6 +2214,7 @@ module IDELAYE2 (...);
     input REGRST;
 endmodule
 
+(* clkbuf_sink = "RDCLK,WRCLK" *)
 module IN_FIFO (...);
     parameter integer ALMOST_EMPTY_VALUE = 1;
     parameter integer ALMOST_FULL_VALUE = 1;
@@ -2191,6 +2251,7 @@ module IN_FIFO (...);
     input [7:0] D6;
 endmodule
 
+(* iopad_external_pin = "IO" *)
 module IOBUF (...);
     parameter integer DRIVE = 12;
     parameter IBUF_LOW_PWR = "TRUE";
@@ -2201,6 +2262,7 @@ module IOBUF (...);
     input I, T;
 endmodule
 
+(* iopad_external_pin = "IO" *)
 module IOBUF_DCIEN (...);
     parameter integer DRIVE = 12;
     parameter IBUF_LOW_PWR = "TRUE";
@@ -2216,6 +2278,7 @@ module IOBUF_DCIEN (...);
     input T;
 endmodule
 
+(* iopad_external_pin = "IO" *)
 module IOBUF_INTERMDISABLE (...);
     parameter integer DRIVE = 12;
     parameter IBUF_LOW_PWR = "TRUE";
@@ -2231,6 +2294,7 @@ module IOBUF_INTERMDISABLE (...);
     input T;
 endmodule
 
+(* iopad_external_pin = "IO" *)
 module IOBUFDS (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2242,6 +2306,7 @@ module IOBUFDS (...);
     input I, T;
 endmodule
 
+(* iopad_external_pin = "IO,IOB" *)
 module IOBUFDS_DCIEN (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2259,6 +2324,7 @@ module IOBUFDS_DCIEN (...);
     input T;
 endmodule
 
+(* iopad_external_pin = "IO,IOB" *)
 module IOBUFDS_DIFF_OUT (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2273,6 +2339,7 @@ module IOBUFDS_DIFF_OUT (...);
     input TS;
 endmodule
 
+(* iopad_external_pin = "IO,IOB" *)
 module IOBUFDS_DIFF_OUT_DCIEN (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2291,6 +2358,7 @@ module IOBUFDS_DIFF_OUT_DCIEN (...);
     input TS;
 endmodule
 
+(* iopad_external_pin = "IO,IOB" *)
 module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2309,6 +2377,7 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
     input TS;
 endmodule
 
+(* clkbuf_sink = "CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB" *)
 module ISERDESE2 (...);
     parameter DATA_RATE = "DDR";
     parameter integer DATA_WIDTH = 4;
@@ -2529,6 +2598,7 @@ module MMCME2_BASE (...);
     input RST;
 endmodule
 
+(* iopad_external_pin = "O,OB" *)
 module OBUFDS (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter IOSTANDARD = "DEFAULT";
@@ -2537,6 +2607,7 @@ module OBUFDS (...);
     input I;
 endmodule
 
+(* iopad_external_pin = "O" *)
 module OBUFT (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter integer DRIVE = 12;
@@ -2546,6 +2617,7 @@ module OBUFT (...);
     input I, T;
 endmodule
 
+(* iopad_external_pin = "O,OB" *)
 module OBUFTDS (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter IOSTANDARD = "DEFAULT";
@@ -2554,6 +2626,7 @@ module OBUFTDS (...);
     input I, T;
 endmodule
 
+(* clkbuf_sink = "C" *)
 module ODDR (...);
     output Q;
     input C;
@@ -2572,6 +2645,7 @@ module ODDR (...);
     parameter XON = "TRUE";
 endmodule
 
+(* clkbuf_sink = "C" *)
 module ODELAYE2 (...);
     parameter CINVCTRL_SEL = "FALSE";
     parameter DELAY_SRC = "ODATAIN";
@@ -2598,6 +2672,7 @@ module ODELAYE2 (...);
     input REGRST;
 endmodule
 
+(* clkbuf_sink = "CLK,CLKDIV" *)
 module OSERDESE2 (...);
     parameter DATA_RATE_OQ = "DDR";
     parameter DATA_RATE_TQ = "DDR";
@@ -2653,6 +2728,7 @@ module OSERDESE2 (...);
     input TCE;
 endmodule
 
+(* clkbuf_sink = "RDCLK,WRCLK" *)
 module OUT_FIFO (...);
     parameter integer ALMOST_EMPTY_VALUE = 1;
     parameter integer ALMOST_FULL_VALUE = 1;
@@ -3655,6 +3731,7 @@ module PULLUP (...);
     output O;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 module RAM128X1S (...);
     parameter [127:0] INIT = 128'h00000000000000000000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3662,6 +3739,7 @@ module RAM128X1S (...);
     input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 module RAM256X1S (...);
     parameter [255:0] INIT = 256'h0;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3672,6 +3750,7 @@ module RAM256X1S (...);
     input WE;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 module RAM32M (...);
     parameter [63:0] INIT_A = 64'h0000000000000000;
     parameter [63:0] INIT_B = 64'h0000000000000000;
@@ -3694,6 +3773,7 @@ module RAM32M (...);
     input WE;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 module RAM32X1S (...);
     parameter [31:0] INIT = 32'h00000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3701,6 +3781,7 @@ module RAM32X1S (...);
     input A0, A1, A2, A3, A4, D, WCLK, WE;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 module RAM32X1S_1 (...);
     parameter [31:0] INIT = 32'h00000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3708,6 +3789,7 @@ module RAM32X1S_1 (...);
     input A0, A1, A2, A3, A4, D, WCLK, WE;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 module RAM32X2S (...);
     parameter [31:0] INIT_00 = 32'h00000000;
     parameter [31:0] INIT_01 = 32'h00000000;
@@ -3716,6 +3798,7 @@ module RAM32X2S (...);
     input A0, A1, A2, A3, A4, D0, D1, WCLK, WE;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 module RAM64M (...);
     parameter [63:0] INIT_A = 64'h0000000000000000;
     parameter [63:0] INIT_B = 64'h0000000000000000;
@@ -3738,6 +3821,7 @@ module RAM64M (...);
     input WE;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 module RAM64X1S (...);
     parameter [63:0] INIT = 64'h0000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3745,6 +3829,7 @@ module RAM64X1S (...);
     input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 module RAM64X1S_1 (...);
     parameter [63:0] INIT = 64'h0000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3752,6 +3837,7 @@ module RAM64X1S_1 (...);
     input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
 endmodule
 
+(* clkbuf_sink = "WCLK" *)
 module RAM64X2S (...);
     parameter [63:0] INIT_00 = 64'h0000000000000000;
     parameter [63:0] INIT_01 = 64'h0000000000000000;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d143c6823..a7362d26b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -63,6 +63,9 @@ struct SynthXilinxPass : public ScriptPass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
+		log("    -ise\n");
+		log("        generate an output netlist suitable for ISE\n");
+		log("\n");
 		log("    -nobram\n");
 		log("        disable inference of block rams\n");
 		log("\n");
@@ -78,6 +81,12 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -nowidelut\n");
 		log("        do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
 		log("\n");
+		log("    -iopads\n");
+		log("        perform I/O buffer insertion (selected automatically by -ise)\n");
+		log("\n");
+		log("    -noiopads\n");
+		log("        disable I/O buffer insertion (only useful with -ise)\n");
+		log("\n");
 		log("    -widemux <int>\n");
 		log("        enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
 		log("        above this number of inputs (minimum value 2, recommended value >= 5).\n");
@@ -104,7 +113,7 @@ struct SynthXilinxPass : public ScriptPass
 	}
 
 	std::string top_opt, edif_file, blif_file, family;
-	bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
+	bool flatten, retime, vpr, ise, iopads, noiopads, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
 	int widemux;
 
 	void clear_flags() YS_OVERRIDE
@@ -116,6 +125,9 @@ struct SynthXilinxPass : public ScriptPass
 		flatten = false;
 		retime = false;
 		vpr = false;
+		ise = false;
+		iopads = false;
+		noiopads = false;
 		nocarry = false;
 		nobram = false;
 		nodram = false;
@@ -178,6 +190,18 @@ struct SynthXilinxPass : public ScriptPass
 				vpr = true;
 				continue;
 			}
+			if (args[argidx] == "-ise") {
+				ise = true;
+				continue;
+			}
+			if (args[argidx] == "-iopads") {
+				iopads = true;
+				continue;
+			}
+			if (args[argidx] == "-noiopads") {
+				noiopads = true;
+				continue;
+			}
 			if (args[argidx] == "-nocarry") {
 				nocarry = true;
 				continue;
@@ -410,6 +434,17 @@ struct SynthXilinxPass : public ScriptPass
 			run("clean");
 		}
 
+		if (check_label("finalize")) {
+			bool do_iopads = iopads || (ise && !noiopads);
+			if (help_mode || do_iopads)
+				run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(-inpad passed if '-iopads' or '-ise' and not '-noiopads')");
+			else
+				run("clkbufmap -buf BUFG O:I");
+
+			if (do_iopads)
+				run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopads' or '-ise' and not '-noiopads')");
+		}
+
 		if (check_label("check")) {
 			run("hierarchy -check");
 			run("stat -tech xilinx");
diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v
index eb1a29579..1287e2c53 100644
--- a/techlibs/xilinx/xc6s_brams_bb.v
+++ b/techlibs/xilinx/xc6s_brams_bb.v
@@ -1,3 +1,4 @@
+(* clkbuf_sink = "CLKAWRCLK,CLKBRDCLK" *)
 module RAMB8BWER (
 	input CLKAWRCLK,
 	input CLKBRDCLK,
@@ -86,6 +87,7 @@ module RAMB8BWER (
 	parameter SIM_COLLISION_CHECK = "ALL";
 endmodule
 
+(* clkbuf_sink = "CLKA,CLKB" *)
 module RAMB16BWER (
 	input CLKA,
 	input CLKB,
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v
index a682ba4a7..046a8fa26 100644
--- a/techlibs/xilinx/xc7_brams_bb.v
+++ b/techlibs/xilinx/xc7_brams_bb.v
@@ -1,3 +1,4 @@
+(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *)
 module RAMB18E1 (
 	input CLKARDCLK,
 	input CLKBWRCLK,
@@ -122,6 +123,7 @@ module RAMB18E1 (
 	parameter SIM_DEVICE = "VIRTEX6";
 endmodule
 
+(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *)
 module RAMB36E1 (
 	input CLKARDCLK,
 	input CLKBWRCLK,

From c6d5b97b98e6edc395ee14ad60430f7ebc264f01 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Tue, 13 Aug 2019 00:35:54 +0000
Subject: [PATCH 035/111] review fixes

---
 CHANGELOG                       |  3 +++
 passes/techmap/clkbufmap.cc     | 18 +++----------
 passes/techmap/iopadmap.cc      | 15 +----------
 techlibs/xilinx/synth_xilinx.cc | 45 ++++++++++++++++++++-------------
 4 files changed, 34 insertions(+), 47 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index 638c36121..56e5c9017 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -19,6 +19,9 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added automatic gzip compression (based on filename extension) for backends
     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
       bit vectors and strings containing [01xz]*
+    - Added "clkbufmap" pass
+    - Added "synth_xilinx -ise" for Spartan 6 (experimental)
+    - "synth_xilinx" now automatically inserts clock buffers
 
 Yosys 0.8 .. Yosys 0.8-dev
 --------------------------
diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc
index 9ecc83071..a2d10c48b 100644
--- a/passes/techmap/clkbufmap.cc
+++ b/passes/techmap/clkbufmap.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2019  Marcin Kościelnicki <mwk@0x04.net>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -32,19 +33,6 @@ void split_portname_pair(std::string &port1, std::string &port2)
 	}
 }
 
-std::vector<std::string> split(std::string text, const char *delim)
-{
-	std::vector<std::string> list;
-	char *p = strdup(text.c_str());
-	char *t = strtok(p, delim);
-	while (t != NULL) {
-		list.push_back(t);
-		t = strtok(NULL, delim);
-	}
-	free(p);
-	return list;
-}
-
 struct ClkbufmapPass : public Pass {
 	ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { }
 	void help() YS_OVERRIDE
@@ -127,7 +115,7 @@ struct ClkbufmapPass : public Pass {
 				auto it = module->attributes.find("\\clkbuf_driver");
 				if (it != module->attributes.end()) {
 					auto value = it->second.decode_string();
-					for (auto name : split(value, ",")) {
+					for (auto name : split_tokens(value, ",")) {
 						auto wire = module->wire(RTLIL::escape_id(name));
 						if (!wire)
 							log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
@@ -138,7 +126,7 @@ struct ClkbufmapPass : public Pass {
 				it = module->attributes.find("\\clkbuf_sink");
 				if (it != module->attributes.end()) {
 					auto value = it->second.decode_string();
-					for (auto name : split(value, ",")) {
+					for (auto name : split_tokens(value, ",")) {
 						auto wire = module->wire(RTLIL::escape_id(name));
 						if (!wire)
 							log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index e3d68ab0c..0fcb6b2ec 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -32,19 +32,6 @@ void split_portname_pair(std::string &port1, std::string &port2)
 	}
 }
 
-std::vector<std::string> split(std::string text, const char *delim)
-{
-	std::vector<std::string> list;
-	char *p = strdup(text.c_str());
-	char *t = strtok(p, delim);
-	while (t != NULL) {
-		list.push_back(t);
-		t = strtok(NULL, delim);
-	}
-	free(p);
-	return list;
-}
-
 struct IopadmapPass : public Pass {
 	IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
 	void help() YS_OVERRIDE
@@ -190,7 +177,7 @@ struct IopadmapPass : public Pass {
 			auto it = module->attributes.find("\\iopad_external_pin");
 			if (it != module->attributes.end()) {
 				auto value = it->second.decode_string();
-				for (auto name : split(value, ",")) {
+				for (auto name : split_tokens(value, ",")) {
 					ignore.insert(make_pair(module->name, RTLIL::escape_id(name)));
 				}
 			}
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a7362d26b..e9e8dbfea 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -81,12 +81,15 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -nowidelut\n");
 		log("        do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
 		log("\n");
-		log("    -iopads\n");
-		log("        perform I/O buffer insertion (selected automatically by -ise)\n");
+		log("    -iopad\n");
+		log("        enable I/O buffer insertion (selected automatically by -ise)\n");
 		log("\n");
-		log("    -noiopads\n");
+		log("    -noiopad\n");
 		log("        disable I/O buffer insertion (only useful with -ise)\n");
 		log("\n");
+		log("    -noclkbuf\n");
+		log("        disable automatic clock buffer insertion\n");
+		log("\n");
 		log("    -widemux <int>\n");
 		log("        enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
 		log("        above this number of inputs (minimum value 2, recommended value >= 5).\n");
@@ -113,7 +116,7 @@ struct SynthXilinxPass : public ScriptPass
 	}
 
 	std::string top_opt, edif_file, blif_file, family;
-	bool flatten, retime, vpr, ise, iopads, noiopads, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
+	bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
 	int widemux;
 
 	void clear_flags() YS_OVERRIDE
@@ -126,8 +129,9 @@ struct SynthXilinxPass : public ScriptPass
 		retime = false;
 		vpr = false;
 		ise = false;
-		iopads = false;
-		noiopads = false;
+		iopad = false;
+		noiopad = false;
+		noclkbuf = false;
 		nocarry = false;
 		nobram = false;
 		nodram = false;
@@ -194,12 +198,16 @@ struct SynthXilinxPass : public ScriptPass
 				ise = true;
 				continue;
 			}
-			if (args[argidx] == "-iopads") {
-				iopads = true;
+			if (args[argidx] == "-iopad") {
+				iopad = true;
 				continue;
 			}
-			if (args[argidx] == "-noiopads") {
-				noiopads = true;
+			if (args[argidx] == "-noiopad") {
+				noiopad = true;
+				continue;
+			}
+			if (args[argidx] == "-noclkbuf") {
+				noclkbuf = true;
 				continue;
 			}
 			if (args[argidx] == "-nocarry") {
@@ -435,14 +443,15 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("finalize")) {
-			bool do_iopads = iopads || (ise && !noiopads);
-			if (help_mode || do_iopads)
-				run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(-inpad passed if '-iopads' or '-ise' and not '-noiopads')");
-			else
-				run("clkbufmap -buf BUFG O:I");
-
-			if (do_iopads)
-				run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopads' or '-ise' and not '-noiopads')");
+			bool do_iopad = iopad || (ise && !noiopad);
+			if (help_mode || !noclkbuf) {
+				if (help_mode || do_iopad)
+					run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(skip if '-noclkbuf', '-inpad' passed if '-iopad' or '-ise' and not '-noiopad')");
+				else
+					run("clkbufmap -buf BUFG O:I");
+			}
+			if (do_iopad)
+				run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
 		}
 
 		if (check_label("check")) {

From 49765ec19ea63bff5f04e28e5729d5852a2f8287 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Tue, 13 Aug 2019 18:05:49 +0000
Subject: [PATCH 036/111] minor review fixes

---
 CHANGELOG                       | 6 ++++--
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index 56e5c9017..bd4cd1b1b 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -20,8 +20,10 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Improve attribute and parameter encoding in JSON to avoid ambiguities between
       bit vectors and strings containing [01xz]*
     - Added "clkbufmap" pass
-    - Added "synth_xilinx -ise" for Spartan 6 (experimental)
-    - "synth_xilinx" now automatically inserts clock buffers
+    - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
+    - Added "synth_xilinx -ise" (experimental)
+    - Added "synth_xilinx -iopad"
+    - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
 
 Yosys 0.8 .. Yosys 0.8-dev
 --------------------------
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e9e8dbfea..4069094a6 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -64,7 +64,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
 		log("    -ise\n");
-		log("        generate an output netlist suitable for ISE\n");
+		log("        generate an output netlist suitable for ISE (enables -iopad)\n");
 		log("\n");
 		log("    -nobram\n");
 		log("        disable inference of block rams\n");

From 3c75a72feb1cf83fa8fc138aa69155446b6b74f0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Tue, 13 Aug 2019 19:36:59 +0000
Subject: [PATCH 037/111] move attributes to wires

---
 passes/techmap/clkbufmap.cc     |  24 +--
 passes/techmap/iopadmap.cc      |  13 +-
 techlibs/xilinx/cells_sim.v     |  75 +++----
 techlibs/xilinx/cells_xtra.py   | 257 ++++++++++++++++++++++++
 techlibs/xilinx/cells_xtra.sh   | 155 ---------------
 techlibs/xilinx/cells_xtra.v    | 339 ++++++++++++++++++++++----------
 techlibs/xilinx/xc6s_brams_bb.v |   6 +-
 techlibs/xilinx/xc7_brams_bb.v  |   6 +-
 8 files changed, 555 insertions(+), 320 deletions(-)
 create mode 100644 techlibs/xilinx/cells_xtra.py
 delete mode 100644 techlibs/xilinx/cells_xtra.sh

diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc
index a2d10c48b..6fac1b437 100644
--- a/passes/techmap/clkbufmap.cc
+++ b/passes/techmap/clkbufmap.cc
@@ -112,27 +112,13 @@ struct ClkbufmapPass : public Pass {
 		for (auto module : modules_sorted)
 		{
 			if (module->get_blackbox_attribute()) {
-				auto it = module->attributes.find("\\clkbuf_driver");
-				if (it != module->attributes.end()) {
-					auto value = it->second.decode_string();
-					for (auto name : split_tokens(value, ",")) {
-						auto wire = module->wire(RTLIL::escape_id(name));
-						if (!wire)
-							log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
+				for (auto wire : module->wires()) {
+					if (wire->get_bool_attribute("\\clkbuf_driver"))
 						for (int i = 0; i < GetSize(wire); i++)
-							buf_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i)));
-					}
-				}
-				it = module->attributes.find("\\clkbuf_sink");
-				if (it != module->attributes.end()) {
-					auto value = it->second.decode_string();
-					for (auto name : split_tokens(value, ",")) {
-						auto wire = module->wire(RTLIL::escape_id(name));
-						if (!wire)
-							log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
+							buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
+					if (wire->get_bool_attribute("\\clkbuf_sink"))
 						for (int i = 0; i < GetSize(wire); i++)
-							sink_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i)));
-					}
+							sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
 				}
 				continue;
 			}
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 0fcb6b2ec..5fe965600 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -173,15 +173,10 @@ struct IopadmapPass : public Pass {
 			ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname4)));
 
 		for (auto module : design->modules())
-		{
-			auto it = module->attributes.find("\\iopad_external_pin");
-			if (it != module->attributes.end()) {
-				auto value = it->second.decode_string();
-				for (auto name : split_tokens(value, ",")) {
-					ignore.insert(make_pair(module->name, RTLIL::escape_id(name)));
-				}
-			}
-		}
+			if (module->get_blackbox_attribute())
+				for (auto wire : module->wires())
+					if (wire->get_bool_attribute("\\iopad_external_pin"))
+						ignore.insert(make_pair(module->name, wire->name));
 
 		for (auto module : design->selected_modules())
 		{
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index d5815ca77..27511a05f 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -29,26 +29,35 @@ module GND(output G);
   assign G = 0;
 endmodule
 
-module IBUF(output O, input I);
+module IBUF(
+    output O,
+    (* iopad_external_pin *)
+    input I);
   parameter IOSTANDARD = "default";
   parameter IBUF_LOW_PWR = 0;
   assign O = I;
 endmodule
 
-module OBUF(output O, input I);
+module OBUF(
+    (* iopad_external_pin *)
+    output O,
+    input I);
   parameter IOSTANDARD = "default";
   parameter DRIVE = 12;
   parameter SLEW = "SLOW";
   assign O = I;
 endmodule
 
-(* clkbuf_driver = "O" *)
-module BUFG(output O, input I);
+module BUFG(
+    (* clkbuf_driver *)
+    output O,
+    input I);
+
   assign O = I;
 endmodule
 
-(* clkbuf_driver = "O" *)
 module BUFGCTRL(
+    (* clkbuf_driver *)
     output O,
     input I0, input I1,
     input S0, input S1,
@@ -74,8 +83,11 @@ assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
 
 endmodule
 
-(* clkbuf_driver = "O" *)
-module BUFHCE(output O, input I, input CE);
+module BUFHCE(
+    (* clkbuf_driver *)
+    output O,
+    input I,
+    input CE);
 
 parameter [0:0] INIT_OUT = 1'b0;
 parameter CE_TYPE = "SYNC";
@@ -216,8 +228,7 @@ endmodule
 
 `endif
 
-(* clkbuf_sink = "C" *)
-module FDRE (output reg Q, input C, CE, D, R);
+module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -229,8 +240,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   endcase endgenerate
 endmodule
 
-(* clkbuf_sink = "C" *)
-module FDSE (output reg Q, input C, CE, D, S);
+module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -242,8 +252,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   endcase endgenerate
 endmodule
 
-(* clkbuf_sink = "C" *)
-module FDCE (output reg Q, input C, CE, D, CLR);
+module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -257,8 +266,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   endcase endgenerate
 endmodule
 
-(* clkbuf_sink = "C" *)
-module FDPE (output reg Q, input C, CE, D, PRE);
+module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -272,39 +280,36 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   endcase endgenerate
 endmodule
 
-(* clkbuf_sink = "C" *)
-module FDRE_1 (output reg Q, input C, CE, D, R);
+module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
-(* clkbuf_sink = "C" *)
-module FDSE_1 (output reg Q, input C, CE, D, S);
+module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
-(* clkbuf_sink = "C" *)
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
+module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-(* clkbuf_sink = "C" *)
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
+module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 (* abc_box_id = 5, abc_scc_break="D,WE" *)
 module RAM32X1D (
   output DPO, SPO,
-  input  D, WCLK, WE,
+  (* clkbuf_sink *)
+  input  WCLK,
+  input  D, WE,
   input  A0, A1, A2, A3, A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
@@ -319,11 +324,12 @@ module RAM32X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 (* abc_box_id = 6, abc_scc_break="D,WE" *)
 module RAM64X1D (
   output DPO, SPO,
-  input  D, WCLK, WE,
+  (* clkbuf_sink *)
+  input  WCLK,
+  input  D, WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
@@ -338,11 +344,12 @@ module RAM64X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 (* abc_box_id = 7, abc_scc_break="D,WE" *)
 module RAM128X1D (
   output       DPO, SPO,
-  input        D, WCLK, WE,
+  input        D, WE,
+  (* clkbuf_sink *)
+  input        WCLK,
   input  [6:0] A, DPRA
 );
   parameter INIT = 128'h0;
@@ -354,10 +361,11 @@ module RAM128X1D (
   always @(posedge clk) if (WE) mem[A] <= D;
 endmodule
 
-(* clkbuf_sink = "CLK" *)
 module SRL16E (
   output Q,
-  input A0, A1, A2, A3, CE, CLK, D
+  (* clkbuf_sink *)
+  input CLK,
+  input A0, A1, A2, A3, CE, D
 );
   parameter [15:0] INIT = 16'h0000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -373,12 +381,13 @@ module SRL16E (
   endgenerate
 endmodule
 
-(* clkbuf_sink = "CLK" *)
 module SRLC32E (
   output Q,
   output Q31,
   input [4:0] A,
-  input CE, CLK, D
+  (* clkbuf_sink *)
+  input CLK,
+  input CE, D
 );
   parameter [31:0] INIT = 32'h00000000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
new file mode 100644
index 000000000..dd4e300ae
--- /dev/null
+++ b/techlibs/xilinx/cells_xtra.py
@@ -0,0 +1,257 @@
+#!/usr/bin/env python3
+
+from argparse import ArgumentParser
+from io import StringIO
+from enum import Enum, auto
+import os.path
+import sys
+
+
+class Cell:
+    def __init__(self, name, keep=False, port_attrs={}):
+        self.name = name
+        self.keep = keep
+        self.port_attrs = port_attrs
+
+
+CELLS = [
+    # Design elements types listed in Xilinx UG953
+    Cell('BSCANE2', keep=True),
+    # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
+    #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
+    #Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('CAPTUREE2', keep=True),
+    # Cell('CARRY4'),
+    Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+    Cell('DCIRESET', keep=True),
+    Cell('DNA_PORT'),
+    Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
+    Cell('EFUSE_USR'),
+    # Cell('FDCE'),
+    # Cell('FDPE'),
+    # Cell('FDRE'),
+    # Cell('FDSE'),
+    Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('FRAME_ECCE2'),
+    Cell('GTHE2_CHANNEL'),
+    Cell('GTHE2_COMMON'),
+    Cell('GTPE2_CHANNEL'),
+    Cell('GTPE2_COMMON'),
+    Cell('GTXE2_CHANNEL'),
+    Cell('GTXE2_COMMON'),
+    # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('ICAPE2', keep=True),
+    Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
+    Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
+    Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
+    Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}),
+    Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('ISERDESE2', port_attrs={
+        'CLK': ['clkbuf_sink'],
+        'CLKB': ['clkbuf_sink'],
+        'OCLK': ['clkbuf_sink'],
+        'OCLKB': ['clkbuf_sink'],
+        'CLKDIV': ['clkbuf_sink'],
+        'CLKDIVP': ['clkbuf_sink'],
+    }),
+    Cell('KEEPER'),
+    Cell('LDCE'),
+    Cell('LDPE'),
+    # Cell('LUT1'),
+    # Cell('LUT2'),
+    # Cell('LUT3'),
+    # Cell('LUT4'),
+    # Cell('LUT5'),
+    # Cell('LUT6'),
+    #Cell('LUT6_2'),
+    Cell('MMCME2_ADV'),
+    Cell('MMCME2_BASE'),
+    # Cell('MUXF7'),
+    # Cell('MUXF8'),
+    # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
+    Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+    Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
+    Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}),
+    Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
+    Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('PHASER_IN'),
+    Cell('PHASER_IN_PHY'),
+    Cell('PHASER_OUT'),
+    Cell('PHASER_OUT_PHY'),
+    Cell('PHASER_REF'),
+    Cell('PHY_CONTROL'),
+    Cell('PLLE2_ADV'),
+    Cell('PLLE2_BASE'),
+    Cell('PS7', keep=True),
+    Cell('PULLDOWN'),
+    Cell('PULLUP'),
+    #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+    # Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+    Cell('ROM128X1'),
+    Cell('ROM256X1'),
+    Cell('ROM32X1'),
+    Cell('ROM64X1'),
+    #Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
+    #Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
+    Cell('STARTUPE2', keep=True),
+    Cell('USR_ACCESSE2'),
+    Cell('XADC'),
+]
+
+class State(Enum):
+    OUTSIDE = auto()
+    IN_MODULE = auto()
+    IN_OTHER_MODULE = auto()
+    IN_FUNCTION = auto()
+    IN_TASK = auto()
+
+def xtract_cell_decl(cell, dirs, outf):
+    for dir in dirs:
+        fname = os.path.join(dir, cell.name + '.v')
+        try:
+            with open(fname) as f:
+                state = State.OUTSIDE
+                found = False
+                # Probably the most horrible Verilog "parser" ever written.
+                for l in f:
+                    l = l.partition('//')[0]
+                    l = l.strip()
+                    if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
+                        if found:
+                            print('Multiple modules in {}.'.format(fname))
+                            sys.exit(1)
+                        elif state != State.OUTSIDE:
+                            print('Nested modules in {}.'.format(fname))
+                            sys.exit(1)
+                        found = True
+                        state = State.IN_MODULE
+                        if cell.keep:
+                            outf.write('(* keep *)\n')
+                        outf.write('module {} (...);\n'.format(cell.name))
+                    elif l.startswith('module '):
+                        if state != State.OUTSIDE:
+                            print('Nested modules in {}.'.format(fname))
+                            sys.exit(1)
+                        state = State.IN_OTHER_MODULE
+                    elif l.startswith('task '):
+                        if state == State.IN_MODULE:
+                            state = State.IN_TASK
+                    elif l.startswith('function '):
+                        if state == State.IN_MODULE:
+                            state = State.IN_FUNCTION
+                    elif l == 'endtask':
+                        if state == State.IN_TASK:
+                            state = State.IN_MODULE
+                    elif l == 'endfunction':
+                        if state == State.IN_FUNCTION:
+                            state = State.IN_MODULE
+                    elif l == 'endmodule':
+                        if state == State.IN_MODULE:
+                            outf.write(l + '\n')
+                            outf.write('\n')
+                        elif state != State.IN_OTHER_MODULE:
+                            print('endmodule in weird place in {}.'.format(cell.name, fname))
+                            sys.exit(1)
+                        state = State.OUTSIDE
+                    elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
+                        if l.endswith((';', ',')):
+                            l = l[:-1]
+                        if ';' in l:
+                            print('Weird port line in {} [{}].'.format(fname, l))
+                            sys.exit(1)
+                        kind, _, ports = l.partition(' ')
+                        for port in ports.split(','):
+                            port = port.strip()
+                            for attr in cell.port_attrs.get(port, []):
+                                outf.write('    (* {} *)\n'.format(attr))
+                            outf.write('    {} {};\n'.format(kind, port))
+                    elif l.startswith('parameter ') and state == State.IN_MODULE:
+                        if 'UNPLACED' in l:
+                            continue
+                        if l.endswith((';', ',')):
+                            l = l[:-1]
+                        while '  ' in l:
+                            l = l.replace('  ', ' ')
+                        if ';' in l:
+                            print('Weird parameter line in {} [{}].'.format(fname, l))
+                            sys.exit(1)
+                        outf.write('    {};\n'.format(l))
+                if state != State.OUTSIDE:
+                    print('endmodule not found in {}.'.format(fname))
+                    sys.exit(1)
+                if not found:
+                    print('Cannot find module {} in {}.'.format(cell.name, fname))
+                    sys.exit(1)
+            return
+        except FileNotFoundError:
+            continue
+    print('Cannot find {}.'.format(cell.name))
+    sys.exit(1)
+
+if __name__ == '__main__':
+    parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from Vivado.')
+    parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1')
+    args = parser.parse_args()
+
+    dirs = [
+        os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'),
+        os.path.join(args.vivado_dir, 'data/verilog/src/retarget'),
+    ]
+    for dir in dirs:
+        if not os.path.isdir(dir):
+            print('{} is not a directory'.format(dir))
+
+    out = StringIO()
+    for cell in CELLS:
+        xtract_cell_decl(cell, dirs, out)
+
+    with open('cells_xtra.v', 'w') as f:
+        f.write('// Created by cells_xtra.py from Xilinx models\n')
+        f.write('\n')
+        f.write(out.getvalue())
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
deleted file mode 100644
index 3291e46a8..000000000
--- a/techlibs/xilinx/cells_xtra.sh
+++ /dev/null
@@ -1,155 +0,0 @@
-#!/bin/bash
-
-set -e
-if [ -z "$1" ]
-then
-	libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src"
-else
-	libdir=$1
-fi
-
-function xtract_cell_decl()
-{
-	for dir in $libdir/xeclib $libdir/retarget; do
-		[ -f $dir/$1.v ] || continue
-		[ -z "$2" ] || echo $2
-		egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
-			sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
-			         s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
-			         s/\s+$//; s/,$/;/; /input|output|parameter/ s/[^;]$/&;/; s/\s+/ /g;
-				 s/^ ((end)?module)/\1/; s/^ /    /; /module.*_bb/,/endmodule/ d;'
-		echo; return
-	done
-	echo "Can't find $1."
-	exit 1
-}
-
-{
-	echo "// Created by cells_xtra.sh from Xilinx models"
-	echo
-
-	# Design elements types listed in Xilinx UG953
-	xtract_cell_decl BSCANE2 "(* keep *)"
-	# xtract_cell_decl BUFG "(* clkbuf_driver = \"O\" *)"
-	xtract_cell_decl BUFGCE "(* clkbuf_driver = \"O\" *)"
-	xtract_cell_decl BUFGCE_1 "(* clkbuf_driver = \"O\" *)"
-	#xtract_cell_decl BUFGCTRL "(* clkbuf_driver = \"O\" *)"
-	xtract_cell_decl BUFGMUX "(* clkbuf_driver = \"O\" *)"
-	xtract_cell_decl BUFGMUX_1 "(* clkbuf_driver = \"O\" *)"
-	xtract_cell_decl BUFGMUX_CTRL "(* clkbuf_driver = \"O\" *)"
-	xtract_cell_decl BUFH "(* clkbuf_driver = \"O\" *)"
-	#xtract_cell_decl BUFHCE "(* clkbuf_driver = \"O\" *)"
-	xtract_cell_decl BUFIO "(* clkbuf_driver = \"O\" *)"
-	xtract_cell_decl BUFMR "(* clkbuf_driver = \"O\" *)"
-	xtract_cell_decl BUFMRCE "(* clkbuf_driver = \"O\" *)"
-	xtract_cell_decl BUFR "(* clkbuf_driver = \"O\" *)"
-	xtract_cell_decl CAPTUREE2 "(* keep *)"
-	# xtract_cell_decl CARRY4
-	xtract_cell_decl CFGLUT5 "(* clkbuf_sink = \"CLK\" *)"
-	xtract_cell_decl DCIRESET "(* keep *)"
-	xtract_cell_decl DNA_PORT
-	xtract_cell_decl DSP48E1 "(* clkbuf_sink = \"CLK\" *)"
-	xtract_cell_decl EFUSE_USR
-	# xtract_cell_decl FDCE
-	# xtract_cell_decl FDPE
-	# xtract_cell_decl FDRE
-	# xtract_cell_decl FDSE
-	xtract_cell_decl FIFO18E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
-	xtract_cell_decl FIFO36E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
-	xtract_cell_decl FRAME_ECCE2
-	xtract_cell_decl GTHE2_CHANNEL
-	xtract_cell_decl GTHE2_COMMON
-	xtract_cell_decl GTPE2_CHANNEL
-	xtract_cell_decl GTPE2_COMMON
-	xtract_cell_decl GTXE2_CHANNEL
-	xtract_cell_decl GTXE2_COMMON
-	# xtract_cell_decl IBUF "(* iopad_external_pin = \"I\" *)"
-	xtract_cell_decl IBUF_IBUFDISABLE "(* iopad_external_pin = \"I\" *)"
-	xtract_cell_decl IBUF_INTERMDISABLE "(* iopad_external_pin = \"I\" *)"
-	xtract_cell_decl IBUFDS "(* iopad_external_pin = \"I,IB\" *)"
-	xtract_cell_decl IBUFDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)"
-	xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)"
-	xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)"
-	xtract_cell_decl IBUFDS_GTE2 "(* iopad_external_pin = \"I,IB\" *)"
-	xtract_cell_decl IBUFDS_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)"
-	xtract_cell_decl IBUFDS_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)"
-	xtract_cell_decl IBUFG "(* iopad_external_pin = \"I\" *)"
-	xtract_cell_decl IBUFGDS "(* iopad_external_pin = \"I,IB\" *)"
-	xtract_cell_decl IBUFGDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)"
-	xtract_cell_decl ICAPE2 "(* keep *)"
-	xtract_cell_decl IDDR "(* clkbuf_sink = \"C\" *)"
-	xtract_cell_decl IDDR_2CLK "(* clkbuf_sink = \"C,CB\" *)"
-	xtract_cell_decl IDELAYCTRL "(* keep *) (* clkbuf_sink = \"REFCLK\" *)"
-	xtract_cell_decl IDELAYE2 "(* clkbuf_sink = \"C\" *)"
-	xtract_cell_decl IN_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
-	xtract_cell_decl IOBUF "(* iopad_external_pin = \"IO\" *)"
-	xtract_cell_decl IOBUF_DCIEN "(* iopad_external_pin = \"IO\" *)"
-	xtract_cell_decl IOBUF_INTERMDISABLE "(* iopad_external_pin = \"IO\" *)"
-	xtract_cell_decl IOBUFDS "(* iopad_external_pin = \"IO\" *)"
-	xtract_cell_decl IOBUFDS_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)"
-	xtract_cell_decl IOBUFDS_DIFF_OUT "(* iopad_external_pin = \"IO,IOB\" *)"
-	xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)"
-	xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"IO,IOB\" *)"
-	xtract_cell_decl ISERDESE2 "(* clkbuf_sink = \"CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB\" *)"
-	xtract_cell_decl KEEPER
-	xtract_cell_decl LDCE
-	xtract_cell_decl LDPE
-	# xtract_cell_decl LUT1
-	# xtract_cell_decl LUT2
-	# xtract_cell_decl LUT3
-	# xtract_cell_decl LUT4
-	# xtract_cell_decl LUT5
-	# xtract_cell_decl LUT6
-	#xtract_cell_decl LUT6_2
-	xtract_cell_decl MMCME2_ADV
-	xtract_cell_decl MMCME2_BASE
-	# xtract_cell_decl MUXF7
-	# xtract_cell_decl MUXF8
-	# xtract_cell_decl OBUF "(* iopad_external_pin = \"O\" *)"
-	xtract_cell_decl OBUFDS "(* iopad_external_pin = \"O,OB\" *)"
-	xtract_cell_decl OBUFT "(* iopad_external_pin = \"O\" *)"
-	xtract_cell_decl OBUFTDS "(* iopad_external_pin = \"O,OB\" *)"
-	xtract_cell_decl ODDR "(* clkbuf_sink = \"C\" *)"
-	xtract_cell_decl ODELAYE2 "(* clkbuf_sink = \"C\" *)"
-	xtract_cell_decl OSERDESE2 "(* clkbuf_sink = \"CLK,CLKDIV\" *)"
-	xtract_cell_decl OUT_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
-	xtract_cell_decl PHASER_IN
-	xtract_cell_decl PHASER_IN_PHY
-	xtract_cell_decl PHASER_OUT
-	xtract_cell_decl PHASER_OUT_PHY
-	xtract_cell_decl PHASER_REF
-	xtract_cell_decl PHY_CONTROL
-	xtract_cell_decl PLLE2_ADV
-	xtract_cell_decl PLLE2_BASE
-	xtract_cell_decl PS7 "(* keep *)"
-	xtract_cell_decl PULLDOWN
-	xtract_cell_decl PULLUP
-	#xtract_cell_decl RAM128X1D "(* clkbuf_sink = \"WCLK\" *)"
-	xtract_cell_decl RAM128X1S "(* clkbuf_sink = \"WCLK\" *)"
-	xtract_cell_decl RAM256X1S "(* clkbuf_sink = \"WCLK\" *)"
-	xtract_cell_decl RAM32M "(* clkbuf_sink = \"WCLK\" *)"
-	#xtract_cell_decl RAM32X1D "(* clkbuf_sink = \"WCLK\" *)"
-	xtract_cell_decl RAM32X1S "(* clkbuf_sink = \"WCLK\" *)"
-	xtract_cell_decl RAM32X1S_1 "(* clkbuf_sink = \"WCLK\" *)"
-	xtract_cell_decl RAM32X2S "(* clkbuf_sink = \"WCLK\" *)"
-	xtract_cell_decl RAM64M "(* clkbuf_sink = \"WCLK\" *)"
-	#xtract_cell_decl RAM64X1D "(* clkbuf_sink = \"WCLK\" *)"
-	xtract_cell_decl RAM64X1S "(* clkbuf_sink = \"WCLK\" *)"
-	xtract_cell_decl RAM64X1S_1 "(* clkbuf_sink = \"WCLK\" *)"
-	xtract_cell_decl RAM64X2S "(* clkbuf_sink = \"WCLK\" *)"
-	# xtract_cell_decl RAMB18E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)"
-	# xtract_cell_decl RAMB36E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)"
-	xtract_cell_decl ROM128X1
-	xtract_cell_decl ROM256X1
-	xtract_cell_decl ROM32X1
-	xtract_cell_decl ROM64X1
-	#xtract_cell_decl SRL16E "(* clkbuf_sink = \"CLK\" *)"
-	#xtract_cell_decl SRLC32E "(* clkbuf_sink = \"CLK\" *)"
-	xtract_cell_decl STARTUPE2 "(* keep *)"
-	xtract_cell_decl USR_ACCESSE2
-	xtract_cell_decl XADC
-} > cells_xtra.new
-
-mv cells_xtra.new cells_xtra.v
-exit 0
-
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 0fbbc0fdf..a6669b872 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -1,4 +1,4 @@
-// Created by cells_xtra.sh from Xilinx models
+// Created by cells_xtra.py from Xilinx models
 
 (* keep *)
 module BSCANE2 (...);
@@ -17,75 +17,79 @@ module BSCANE2 (...);
     input TDO;
 endmodule
 
-(* clkbuf_driver = "O" *)
 module BUFGCE (...);
     parameter CE_TYPE = "SYNC";
     parameter [0:0] IS_CE_INVERTED = 1'b0;
     parameter [0:0] IS_I_INVERTED = 1'b0;
+    (* clkbuf_driver *)
     output O;
     input CE;
     input I;
 endmodule
 
-(* clkbuf_driver = "O" *)
 module BUFGCE_1 (...);
+    (* clkbuf_driver *)
     output O;
     input CE;
     input I;
 endmodule
 
-(* clkbuf_driver = "O" *)
 module BUFGMUX (...);
     parameter CLK_SEL_TYPE = "SYNC";
-    output O;
-    input I0, I1, S;
-endmodule
-
-(* clkbuf_driver = "O" *)
-module BUFGMUX_1 (...);
-    parameter CLK_SEL_TYPE = "SYNC";
-    output O;
-    input I0, I1, S;
-endmodule
-
-(* clkbuf_driver = "O" *)
-module BUFGMUX_CTRL (...);
+    (* clkbuf_driver *)
+    output O;
+    input I0;
+    input I1;
+    input S;
+endmodule
+
+module BUFGMUX_1 (...);
+    parameter CLK_SEL_TYPE = "SYNC";
+    (* clkbuf_driver *)
+    output O;
+    input I0;
+    input I1;
+    input S;
+endmodule
+
+module BUFGMUX_CTRL (...);
+    (* clkbuf_driver *)
     output O;
     input I0;
     input I1;
     input S;
 endmodule
 
-(* clkbuf_driver = "O" *)
 module BUFH (...);
+    (* clkbuf_driver *)
     output O;
     input I;
 endmodule
 
-(* clkbuf_driver = "O" *)
 module BUFIO (...);
+    (* clkbuf_driver *)
     output O;
     input I;
 endmodule
 
-(* clkbuf_driver = "O" *)
 module BUFMR (...);
+    (* clkbuf_driver *)
     output O;
     input I;
 endmodule
 
-(* clkbuf_driver = "O" *)
 module BUFMRCE (...);
     parameter CE_TYPE = "SYNC";
     parameter integer INIT_OUT = 0;
     parameter [0:0] IS_CE_INVERTED = 1'b0;
+    (* clkbuf_driver *)
     output O;
     input CE;
     input I;
 endmodule
 
-(* clkbuf_driver = "O" *)
 module BUFR (...);
+    (* clkbuf_driver *)
     output O;
     input CE;
     input CLR;
@@ -101,15 +105,21 @@ module CAPTUREE2 (...);
     input CLK;
 endmodule
 
-(* clkbuf_sink = "CLK" *)
 module CFGLUT5 (...);
     parameter [31:0] INIT = 32'h00000000;
     parameter [0:0] IS_CLK_INVERTED = 1'b0;
     output CDO;
     output O5;
     output O6;
-    input I4, I3, I2, I1, I0;
-    input CDI, CE, CLK;
+    input I4;
+    input I3;
+    input I2;
+    input I1;
+    input I0;
+    input CDI;
+    input CE;
+    (* clkbuf_sink *)
+    input CLK;
 endmodule
 
 (* keep *)
@@ -121,10 +131,12 @@ endmodule
 module DNA_PORT (...);
     parameter [56:0] SIM_DNA_VALUE = 57'h0;
     output DOUT;
-    input CLK, DIN, READ, SHIFT;
+    input CLK;
+    input DIN;
+    input READ;
+    input SHIFT;
 endmodule
 
-(* clkbuf_sink = "CLK" *)
 module DSP48E1 (...);
     parameter integer ACASCREG = 1;
     parameter integer ADREG = 1;
@@ -189,6 +201,7 @@ module DSP48E1 (...);
     input CEINMODE;
     input CEM;
     input CEP;
+    (* clkbuf_sink *)
     input CLK;
     input [24:0] D;
     input [4:0] INMODE;
@@ -212,7 +225,6 @@ module EFUSE_USR (...);
     output [31:0] EFUSEUSR;
 endmodule
 
-(* clkbuf_sink = "RDCLK,WRCLK" *)
 module FIFO18E1 (...);
     parameter ALMOST_EMPTY_OFFSET = 13'h0080;
     parameter ALMOST_FULL_OFFSET = 13'h0080;
@@ -242,16 +254,17 @@ module FIFO18E1 (...);
     output WRERR;
     input [31:0] DI;
     input [3:0] DIP;
+    (* clkbuf_sink *)
     input RDCLK;
     input RDEN;
     input REGCE;
     input RST;
     input RSTREG;
+    (* clkbuf_sink *)
     input WRCLK;
     input WREN;
 endmodule
 
-(* clkbuf_sink = "RDCLK,WRCLK" *)
 module FIFO36E1 (...);
     parameter ALMOST_EMPTY_OFFSET = 13'h0080;
     parameter ALMOST_FULL_OFFSET = 13'h0080;
@@ -288,11 +301,13 @@ module FIFO36E1 (...);
     input [7:0] DIP;
     input INJECTDBITERR;
     input INJECTSBITERR;
+    (* clkbuf_sink *)
     input RDCLK;
     input RDEN;
     input REGCE;
     input RST;
     input RSTREG;
+    (* clkbuf_sink *)
     input WRCLK;
     input WREN;
 endmodule
@@ -1979,30 +1994,29 @@ module GTXE2_COMMON (...);
     input [7:0] PMARSVD;
 endmodule
 
-(* iopad_external_pin = "I" *)
 module IBUF_IBUFDISABLE (...);
     parameter IBUF_LOW_PWR = "TRUE";
     parameter IOSTANDARD = "DEFAULT";
     parameter SIM_DEVICE = "7SERIES";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     input I;
     input IBUFDISABLE;
 endmodule
 
-(* iopad_external_pin = "I" *)
 module IBUF_INTERMDISABLE (...);
     parameter IBUF_LOW_PWR = "TRUE";
     parameter IOSTANDARD = "DEFAULT";
     parameter SIM_DEVICE = "7SERIES";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     input I;
     input IBUFDISABLE;
     input INTERMDISABLE;
 endmodule
 
-(* iopad_external_pin = "I,IB" *)
 module IBUFDS (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter DIFF_TERM = "FALSE";
@@ -2012,20 +2026,25 @@ module IBUFDS (...);
     parameter IFD_DELAY_VALUE = "AUTO";
     parameter IOSTANDARD = "DEFAULT";
     output O;
-    input I, IB;
+    (* iopad_external_pin *)
+    input I;
+    (* iopad_external_pin *)
+    input IB;
 endmodule
 
-(* iopad_external_pin = "I,IB" *)
 module IBUFDS_DIFF_OUT (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
     parameter IBUF_LOW_PWR = "TRUE";
     parameter IOSTANDARD = "DEFAULT";
-    output O, OB;
-    input I, IB;
+    output O;
+    output OB;
+    (* iopad_external_pin *)
+    input I;
+    (* iopad_external_pin *)
+    input IB;
 endmodule
 
-(* iopad_external_pin = "I,IB" *)
 module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2035,12 +2054,13 @@ module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
     output OB;
+    (* iopad_external_pin *)
     input I;
+    (* iopad_external_pin *)
     input IB;
     input IBUFDISABLE;
 endmodule
 
-(* iopad_external_pin = "I,IB" *)
 module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2050,13 +2070,14 @@ module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
     output OB;
+    (* iopad_external_pin *)
     input I;
+    (* iopad_external_pin *)
     input IB;
     input IBUFDISABLE;
     input INTERMDISABLE;
 endmodule
 
-(* iopad_external_pin = "I,IB" *)
 module IBUFDS_GTE2 (...);
     parameter CLKCM_CFG = "TRUE";
     parameter CLKRCV_TRST = "TRUE";
@@ -2064,11 +2085,12 @@ module IBUFDS_GTE2 (...);
     output O;
     output ODIV2;
     input CEB;
+    (* iopad_external_pin *)
     input I;
+    (* iopad_external_pin *)
     input IB;
 endmodule
 
-(* iopad_external_pin = "I,IB" *)
 module IBUFDS_IBUFDISABLE (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2077,12 +2099,13 @@ module IBUFDS_IBUFDISABLE (...);
     parameter SIM_DEVICE = "7SERIES";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     input I;
+    (* iopad_external_pin *)
     input IB;
     input IBUFDISABLE;
 endmodule
 
-(* iopad_external_pin = "I,IB" *)
 module IBUFDS_INTERMDISABLE (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2091,23 +2114,24 @@ module IBUFDS_INTERMDISABLE (...);
     parameter SIM_DEVICE = "7SERIES";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     input I;
+    (* iopad_external_pin *)
     input IB;
     input IBUFDISABLE;
     input INTERMDISABLE;
 endmodule
 
-(* iopad_external_pin = "I" *)
 module IBUFG (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter IBUF_DELAY_VALUE = "0";
     parameter IBUF_LOW_PWR = "TRUE";
     parameter IOSTANDARD = "DEFAULT";
     output O;
+    (* iopad_external_pin *)
     input I;
 endmodule
 
-(* iopad_external_pin = "I,IB" *)
 module IBUFGDS (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter DIFF_TERM = "FALSE";
@@ -2115,17 +2139,23 @@ module IBUFGDS (...);
     parameter IBUF_LOW_PWR = "TRUE";
     parameter IOSTANDARD = "DEFAULT";
     output O;
-    input I, IB;
+    (* iopad_external_pin *)
+    input I;
+    (* iopad_external_pin *)
+    input IB;
 endmodule
 
-(* iopad_external_pin = "I,IB" *)
 module IBUFGDS_DIFF_OUT (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
     parameter IBUF_LOW_PWR = "TRUE";
     parameter IOSTANDARD = "DEFAULT";
-    output O, OB;
-    input I, IB;
+    output O;
+    output OB;
+    (* iopad_external_pin *)
+    input I;
+    (* iopad_external_pin *)
+    input IB;
 endmodule
 
 (* keep *)
@@ -2140,7 +2170,6 @@ module ICAPE2 (...);
     input [31:0] I;
 endmodule
 
-(* clkbuf_sink = "C" *)
 module IDDR (...);
     parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
     parameter INIT_Q1 = 1'b0;
@@ -2152,6 +2181,7 @@ module IDDR (...);
     parameter XON = "TRUE";
     output Q1;
     output Q2;
+    (* clkbuf_sink *)
     input C;
     input CE;
     input D;
@@ -2159,7 +2189,6 @@ module IDDR (...);
     input S;
 endmodule
 
-(* clkbuf_sink = "C,CB" *)
 module IDDR_2CLK (...);
     parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
     parameter INIT_Q1 = 1'b0;
@@ -2170,7 +2199,9 @@ module IDDR_2CLK (...);
     parameter SRTYPE = "SYNC";
     output Q1;
     output Q2;
+    (* clkbuf_sink *)
     input C;
+    (* clkbuf_sink *)
     input CB;
     input CE;
     input D;
@@ -2178,15 +2209,15 @@ module IDDR_2CLK (...);
     input S;
 endmodule
 
-(* keep *) (* clkbuf_sink = "REFCLK" *)
+(* keep *)
 module IDELAYCTRL (...);
     parameter SIM_DEVICE = "7SERIES";
     output RDY;
+    (* clkbuf_sink *)
     input REFCLK;
     input RST;
 endmodule
 
-(* clkbuf_sink = "C" *)
 module IDELAYE2 (...);
     parameter CINVCTRL_SEL = "FALSE";
     parameter DELAY_SRC = "IDATAIN";
@@ -2202,6 +2233,7 @@ module IDELAYE2 (...);
     parameter integer SIM_DELAY_D = 0;
     output [4:0] CNTVALUEOUT;
     output DATAOUT;
+    (* clkbuf_sink *)
     input C;
     input CE;
     input CINVCTRL;
@@ -2214,7 +2246,6 @@ module IDELAYE2 (...);
     input REGRST;
 endmodule
 
-(* clkbuf_sink = "RDCLK,WRCLK" *)
 module IN_FIFO (...);
     parameter integer ALMOST_EMPTY_VALUE = 1;
     parameter integer ALMOST_FULL_VALUE = 1;
@@ -2234,9 +2265,11 @@ module IN_FIFO (...);
     output [7:0] Q7;
     output [7:0] Q8;
     output [7:0] Q9;
+    (* clkbuf_sink *)
     input RDCLK;
     input RDEN;
     input RESET;
+    (* clkbuf_sink *)
     input WRCLK;
     input WREN;
     input [3:0] D0;
@@ -2251,18 +2284,18 @@ module IN_FIFO (...);
     input [7:0] D6;
 endmodule
 
-(* iopad_external_pin = "IO" *)
 module IOBUF (...);
     parameter integer DRIVE = 12;
     parameter IBUF_LOW_PWR = "TRUE";
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
     output O;
+    (* iopad_external_pin *)
     inout IO;
-    input I, T;
+    input I;
+    input T;
 endmodule
 
-(* iopad_external_pin = "IO" *)
 module IOBUF_DCIEN (...);
     parameter integer DRIVE = 12;
     parameter IBUF_LOW_PWR = "TRUE";
@@ -2271,6 +2304,7 @@ module IOBUF_DCIEN (...);
     parameter SLEW = "SLOW";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     inout IO;
     input DCITERMDISABLE;
     input I;
@@ -2278,7 +2312,6 @@ module IOBUF_DCIEN (...);
     input T;
 endmodule
 
-(* iopad_external_pin = "IO" *)
 module IOBUF_INTERMDISABLE (...);
     parameter integer DRIVE = 12;
     parameter IBUF_LOW_PWR = "TRUE";
@@ -2287,6 +2320,7 @@ module IOBUF_INTERMDISABLE (...);
     parameter SLEW = "SLOW";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     inout IO;
     input I;
     input IBUFDISABLE;
@@ -2294,7 +2328,6 @@ module IOBUF_INTERMDISABLE (...);
     input T;
 endmodule
 
-(* iopad_external_pin = "IO" *)
 module IOBUFDS (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2302,11 +2335,13 @@ module IOBUFDS (...);
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
     output O;
-    inout IO, IOB;
-    input I, T;
+    (* iopad_external_pin *)
+    inout IO;
+    inout IOB;
+    input I;
+    input T;
 endmodule
 
-(* iopad_external_pin = "IO,IOB" *)
 module IOBUFDS_DCIEN (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2316,7 +2351,9 @@ module IOBUFDS_DCIEN (...);
     parameter SLEW = "SLOW";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     inout IO;
+    (* iopad_external_pin *)
     inout IOB;
     input DCITERMDISABLE;
     input I;
@@ -2324,7 +2361,6 @@ module IOBUFDS_DCIEN (...);
     input T;
 endmodule
 
-(* iopad_external_pin = "IO,IOB" *)
 module IOBUFDS_DIFF_OUT (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2332,14 +2368,15 @@ module IOBUFDS_DIFF_OUT (...);
     parameter IOSTANDARD = "DEFAULT";
     output O;
     output OB;
+    (* iopad_external_pin *)
     inout IO;
+    (* iopad_external_pin *)
     inout IOB;
     input I;
     input TM;
     input TS;
 endmodule
 
-(* iopad_external_pin = "IO,IOB" *)
 module IOBUFDS_DIFF_OUT_DCIEN (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2349,7 +2386,9 @@ module IOBUFDS_DIFF_OUT_DCIEN (...);
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
     output OB;
+    (* iopad_external_pin *)
     inout IO;
+    (* iopad_external_pin *)
     inout IOB;
     input DCITERMDISABLE;
     input I;
@@ -2358,7 +2397,6 @@ module IOBUFDS_DIFF_OUT_DCIEN (...);
     input TS;
 endmodule
 
-(* iopad_external_pin = "IO,IOB" *)
 module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
     parameter DIFF_TERM = "FALSE";
     parameter DQS_BIAS = "FALSE";
@@ -2368,7 +2406,9 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
     output OB;
+    (* iopad_external_pin *)
     inout IO;
+    (* iopad_external_pin *)
     inout IOB;
     input I;
     input IBUFDISABLE;
@@ -2377,7 +2417,6 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
     input TS;
 endmodule
 
-(* clkbuf_sink = "CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB" *)
 module ISERDESE2 (...);
     parameter DATA_RATE = "DDR";
     parameter integer DATA_WIDTH = 4;
@@ -2417,15 +2456,21 @@ module ISERDESE2 (...);
     input BITSLIP;
     input CE1;
     input CE2;
+    (* clkbuf_sink *)
     input CLK;
+    (* clkbuf_sink *)
     input CLKB;
+    (* clkbuf_sink *)
     input CLKDIV;
+    (* clkbuf_sink *)
     input CLKDIVP;
     input D;
     input DDLY;
     input DYNCLKDIVSEL;
     input DYNCLKSEL;
+    (* clkbuf_sink *)
     input OCLK;
+    (* clkbuf_sink *)
     input OCLKB;
     input OFB;
     input RST;
@@ -2444,7 +2489,10 @@ module LDCE (...);
     parameter MSGON = "TRUE";
     parameter XON = "TRUE";
     output Q;
-    input CLR, D, G, GE;
+    input CLR;
+    input D;
+    input G;
+    input GE;
 endmodule
 
 module LDPE (...);
@@ -2454,7 +2502,10 @@ module LDPE (...);
     parameter MSGON = "TRUE";
     parameter XON = "TRUE";
     output Q;
-    input D, G, GE, PRE;
+    input D;
+    input G;
+    input GE;
+    input PRE;
 endmodule
 
 module MMCME2_ADV (...);
@@ -2598,37 +2649,43 @@ module MMCME2_BASE (...);
     input RST;
 endmodule
 
-(* iopad_external_pin = "O,OB" *)
 module OBUFDS (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
-    output O, OB;
+    (* iopad_external_pin *)
+    output O;
+    (* iopad_external_pin *)
+    output OB;
     input I;
 endmodule
 
-(* iopad_external_pin = "O" *)
 module OBUFT (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter integer DRIVE = 12;
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
+    (* iopad_external_pin *)
     output O;
-    input I, T;
+    input I;
+    input T;
 endmodule
 
-(* iopad_external_pin = "O,OB" *)
 module OBUFTDS (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
-    output O, OB;
-    input I, T;
+    (* iopad_external_pin *)
+    output O;
+    (* iopad_external_pin *)
+    output OB;
+    input I;
+    input T;
 endmodule
 
-(* clkbuf_sink = "C" *)
 module ODDR (...);
     output Q;
+    (* clkbuf_sink *)
     input C;
     input CE;
     input D1;
@@ -2645,7 +2702,6 @@ module ODDR (...);
     parameter XON = "TRUE";
 endmodule
 
-(* clkbuf_sink = "C" *)
 module ODELAYE2 (...);
     parameter CINVCTRL_SEL = "FALSE";
     parameter DELAY_SRC = "ODATAIN";
@@ -2660,6 +2716,7 @@ module ODELAYE2 (...);
     parameter integer SIM_DELAY_D = 0;
     output [4:0] CNTVALUEOUT;
     output DATAOUT;
+    (* clkbuf_sink *)
     input C;
     input CE;
     input CINVCTRL;
@@ -2672,7 +2729,6 @@ module ODELAYE2 (...);
     input REGRST;
 endmodule
 
-(* clkbuf_sink = "CLK,CLKDIV" *)
 module OSERDESE2 (...);
     parameter DATA_RATE_OQ = "DDR";
     parameter DATA_RATE_TQ = "DDR";
@@ -2706,7 +2762,9 @@ module OSERDESE2 (...);
     output TBYTEOUT;
     output TFB;
     output TQ;
+    (* clkbuf_sink *)
     input CLK;
+    (* clkbuf_sink *)
     input CLKDIV;
     input D1;
     input D2;
@@ -2728,7 +2786,6 @@ module OSERDESE2 (...);
     input TCE;
 endmodule
 
-(* clkbuf_sink = "RDCLK,WRCLK" *)
 module OUT_FIFO (...);
     parameter integer ALMOST_EMPTY_VALUE = 1;
     parameter integer ALMOST_FULL_VALUE = 1;
@@ -2749,9 +2806,11 @@ module OUT_FIFO (...);
     output [3:0] Q9;
     output [7:0] Q5;
     output [7:0] Q6;
+    (* clkbuf_sink *)
     input RDCLK;
     input RDEN;
     input RESET;
+    (* clkbuf_sink *)
     input WRCLK;
     input WREN;
     input [7:0] D0;
@@ -3731,26 +3790,34 @@ module PULLUP (...);
     output O;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 module RAM128X1S (...);
     parameter [127:0] INIT = 128'h00000000000000000000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
     output O;
-    input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
+    input D;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 module RAM256X1S (...);
     parameter [255:0] INIT = 256'h0;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
     output O;
     input [7:0] A;
     input D;
+    (* clkbuf_sink *)
     input WCLK;
     input WE;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 module RAM32M (...);
     parameter [63:0] INIT_A = 64'h0000000000000000;
     parameter [63:0] INIT_B = 64'h0000000000000000;
@@ -3769,36 +3836,59 @@ module RAM32M (...);
     input [1:0] DIB;
     input [1:0] DIC;
     input [1:0] DID;
+    (* clkbuf_sink *)
     input WCLK;
     input WE;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 module RAM32X1S (...);
     parameter [31:0] INIT = 32'h00000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
     output O;
-    input A0, A1, A2, A3, A4, D, WCLK, WE;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input D;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 module RAM32X1S_1 (...);
     parameter [31:0] INIT = 32'h00000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
     output O;
-    input A0, A1, A2, A3, A4, D, WCLK, WE;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input D;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 module RAM32X2S (...);
     parameter [31:0] INIT_00 = 32'h00000000;
     parameter [31:0] INIT_01 = 32'h00000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-    output O0, O1;
-    input A0, A1, A2, A3, A4, D0, D1, WCLK, WE;
+    output O0;
+    output O1;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input D0;
+    input D1;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 module RAM64M (...);
     parameter [63:0] INIT_A = 64'h0000000000000000;
     parameter [63:0] INIT_B = 64'h0000000000000000;
@@ -3817,57 +3907,106 @@ module RAM64M (...);
     input DIB;
     input DIC;
     input DID;
+    (* clkbuf_sink *)
     input WCLK;
     input WE;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 module RAM64X1S (...);
     parameter [63:0] INIT = 64'h0000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
     output O;
-    input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input D;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 module RAM64X1S_1 (...);
     parameter [63:0] INIT = 64'h0000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
     output O;
-    input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input D;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
-(* clkbuf_sink = "WCLK" *)
 module RAM64X2S (...);
     parameter [63:0] INIT_00 = 64'h0000000000000000;
     parameter [63:0] INIT_01 = 64'h0000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-    output O0, O1;
-    input A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE;
+    output O0;
+    output O1;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input D0;
+    input D1;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
 module ROM128X1 (...);
     parameter [127:0] INIT = 128'h00000000000000000000000000000000;
     output O;
-    input A0, A1, A2, A3, A4, A5, A6;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
 endmodule
 
 module ROM256X1 (...);
     parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
     output O;
-    input A0, A1, A2, A3, A4, A5, A6, A7;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
+    input A7;
 endmodule
 
 module ROM32X1 (...);
     parameter [31:0] INIT = 32'h00000000;
     output O;
-    input A0, A1, A2, A3, A4;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
 endmodule
 
 module ROM64X1 (...);
     parameter [63:0] INIT = 64'h0000000000000000;
     output O;
-    input A0, A1, A2, A3, A4, A5;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
 endmodule
 
 (* keep *)
diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v
index 1287e2c53..041d6b54f 100644
--- a/techlibs/xilinx/xc6s_brams_bb.v
+++ b/techlibs/xilinx/xc6s_brams_bb.v
@@ -1,6 +1,7 @@
-(* clkbuf_sink = "CLKAWRCLK,CLKBRDCLK" *)
 module RAMB8BWER (
+	(* clkbuf_sink *)
 	input CLKAWRCLK,
+	(* clkbuf_sink *)
 	input CLKBRDCLK,
 	input ENAWREN,
 	input ENBRDEN,
@@ -87,9 +88,10 @@ module RAMB8BWER (
 	parameter SIM_COLLISION_CHECK = "ALL";
 endmodule
 
-(* clkbuf_sink = "CLKA,CLKB" *)
 module RAMB16BWER (
+	(* clkbuf_sink *)
 	input CLKA,
+	(* clkbuf_sink *)
 	input CLKB,
 	input ENA,
 	input ENB,
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v
index 046a8fa26..a43b4b5a1 100644
--- a/techlibs/xilinx/xc7_brams_bb.v
+++ b/techlibs/xilinx/xc7_brams_bb.v
@@ -1,6 +1,7 @@
-(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *)
 module RAMB18E1 (
+	(* clkbuf_sink *)
 	input CLKARDCLK,
+	(* clkbuf_sink *)
 	input CLKBWRCLK,
 	input ENARDEN,
 	input ENBWREN,
@@ -123,9 +124,10 @@ module RAMB18E1 (
 	parameter SIM_DEVICE = "VIRTEX6";
 endmodule
 
-(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *)
 module RAMB36E1 (
+	(* clkbuf_sink *)
 	input CLKARDCLK,
+	(* clkbuf_sink *)
 	input CLKBWRCLK,
 	input ENARDEN,
 	input ENBWREN,

From 2d5d82e2b6f7d369c0d41b499646a8719ff0bc20 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Tue, 13 Aug 2019 21:47:27 +0200
Subject: [PATCH 038/111] README updates

---
 README.md | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/README.md b/README.md
index d9989eb29..767a0fb61 100644
--- a/README.md
+++ b/README.md
@@ -329,6 +329,20 @@ Verilog Attributes and non-standard features
   that represent module parameters or localparams (when the HDL front-end
   is run in -pwires mode).
 
+- The ``clkbuf_inhibit`` attribute can be set on a wire to prevent
+  automatic clock buffer insertion by ``clkbufmap``.
+
+- The ``clkbuf_sink`` attribute can be set on an input port of a blackbox
+  module to request clock buffer insertion by the ``clkbufmap`` pass.
+
+- The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
+  module to mark it as a clock buffer output, and thus prevent ``clkbufmap``
+  from inserting another clock buffer on a net driven by such output.
+
+- The ``iopad_external_pin`` attribute on a blacbox module's port marks
+  it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
+  from inserting another pad cell on it.
+
 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes
   for everything that comes after the ``{* ... *}`` statement. (Reset

From 193eae0c84860c65bd5dd135b7e59c0c11ea76b0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:48:16 -0700
Subject: [PATCH 039/111] techmap -max_iter to apply to each module
 individually

---
 passes/techmap/techmap.cc | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index b271c8781..a6c1214a7 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -943,7 +943,8 @@ struct TechmapPass : public Pass {
 		log("        instead of inlining them.\n");
 		log("\n");
 		log("    -max_iter <number>\n");
-		log("        only run the specified number of iterations.\n");
+		log("        only run the specified number of iterations for each module.\n");
+		log("        default: unlimited\n");
 		log("\n");
 		log("    -recursive\n");
 		log("        instead of the iterative breadth-first algorithm use a recursive\n");
@@ -1157,15 +1158,16 @@ struct TechmapPass : public Pass {
 			RTLIL::Module *module = *worker.module_queue.begin();
 			worker.module_queue.erase(module);
 
+			int module_max_iter = max_iter;
 			bool did_something = true;
 			std::set<RTLIL::Cell*> handled_cells;
 			while (did_something) {
 				did_something = false;
-					if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
-						did_something = true;
+				if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
+					did_something = true;
 				if (did_something)
 					module->check();
-				if (max_iter > 0 && --max_iter == 0)
+				if (module_max_iter > 0 && --module_max_iter == 0)
 					break;
 			}
 		}

From fce8dc7db20d722646cea83ca841160d3d07445e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 20:05:16 -0700
Subject: [PATCH 040/111] Add test

---
 tests/techmap/recursive.v          | 8 ++++++++
 tests/techmap/recursive_map.v      | 4 ++++
 tests/techmap/recursive_runtest.sh | 3 +++
 3 files changed, 15 insertions(+)
 create mode 100644 tests/techmap/recursive.v
 create mode 100644 tests/techmap/recursive_map.v
 create mode 100644 tests/techmap/recursive_runtest.sh

diff --git a/tests/techmap/recursive.v b/tests/techmap/recursive.v
new file mode 100644
index 000000000..d281b21d8
--- /dev/null
+++ b/tests/techmap/recursive.v
@@ -0,0 +1,8 @@
+module top;
+sub s0();
+foo f0();
+endmodule
+
+module foo;
+sub s0();
+endmodule
diff --git a/tests/techmap/recursive_map.v b/tests/techmap/recursive_map.v
new file mode 100644
index 000000000..934256552
--- /dev/null
+++ b/tests/techmap/recursive_map.v
@@ -0,0 +1,4 @@
+module sub;
+    sub _TECHMAP_REPLACE_ ();
+    bar f0();
+endmodule
diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh
new file mode 100644
index 000000000..30c79bf03
--- /dev/null
+++ b/tests/techmap/recursive_runtest.sh
@@ -0,0 +1,3 @@
+set -ev
+
+../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v

From fe61dcce8b70236b29691fa56c562d17497d3567 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 20:05:51 -0700
Subject: [PATCH 041/111] Grammar

---
 passes/techmap/techmap.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index a6c1214a7..c4496f76f 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -943,7 +943,7 @@ struct TechmapPass : public Pass {
 		log("        instead of inlining them.\n");
 		log("\n");
 		log("    -max_iter <number>\n");
-		log("        only run the specified number of iterations for each module.\n");
+		log("        only run the specified number of iterations on each module.\n");
 		log("        default: unlimited\n");
 		log("\n");
 		log("    -recursive\n");

From 9b9d75945194f98e08b46e8e506832542ebf73ad Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 20:18:51 -0700
Subject: [PATCH 042/111] Fix copy-paste typo

---
 passes/pmgen/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index 790811d4c..382a1b4ad 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -17,7 +17,7 @@ $(eval $(call add_extra_objs,passes/pmgen/ice40_dsp_pm.h))
 
 OBJS += passes/pmgen/ice40_wrapcarry.o
 passes/pmgen/ice40_wrapcarry.o: passes/pmgen/ice40_wrapcarry_pm.h
-$(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h))
+$(eval $(call add_extra_objs,passes/pmgen/ice40_wrapcarry_pm.h))
 
 # --------------------------------------
 

From 076af2e6176ecc440be7b7fa984ea5b461bb95de Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 20:37:52 -0700
Subject: [PATCH 043/111] Missing newline

---
 techlibs/common/synth.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 555de9fba..a176357a7 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -175,7 +175,7 @@ struct SynthPass : public ScriptPass
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		if (abc == "abc9" && !lut)
-			log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)");
+			log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n");
 
 		log_header(design, "Executing SYNTH pass.\n");
 		log_push();

From 948b6f91a140dafa4bd47177769eb4974d08f203 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 21 Aug 2019 17:00:24 +0200
Subject: [PATCH 044/111] Fix test_pmgen deps

---
 passes/pmgen/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index 382a1b4ad..8e0cbdca8 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -4,7 +4,7 @@
 # --------------------------------------
 
 OBJS += passes/pmgen/test_pmgen.o
-passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h
+passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h
 $(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h))
 
 # --------------------------------------

From a6776ee35ee5404ca7d5b63fd2daccc46354112c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 13:36:01 -0700
Subject: [PATCH 045/111] mem2reg to preserve user attributes and src

---
 frontends/ast/simplify.cc |  4 ++++
 tests/various/mem2reg.ys  | 13 +++++++++++++
 2 files changed, 17 insertions(+)
 create mode 100644 tests/various/mem2reg.ys

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 54b9efaad..8493aa513 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -150,6 +150,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 					reg->str = stringf("%s[%d]", node->str.c_str(), i);
 					reg->is_reg = true;
 					reg->is_signed = node->is_signed;
+					for (auto &it : node->attributes)
+						reg->attributes.emplace(it.first, it.second->clone());
+					reg->filename = node->filename;
+					reg->linenum = node->linenum;
 					children.push_back(reg);
 					while (reg->simplify(true, false, false, 1, -1, false, false)) { }
 				}
diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys
new file mode 100644
index 000000000..00389c700
--- /dev/null
+++ b/tests/various/mem2reg.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top;
+parameter DATADEPTH=2;
+parameter DATAWIDTH=1;
+(* keep, nomem2reg *) reg [DATAWIDTH-1:0] data1 [DATADEPTH-1:0];
+(* keep, mem2reg *) reg [DATAWIDTH-1:0] data2 [DATADEPTH-1:0];
+endmodule
+EOT
+
+proc
+cd top
+select -assert-count 1 m:data1 a:src=<<EOT:4 %i
+select -assert-count 2 w:data2[*] a:src=<<EOT:5 %i

From d3a212ff91de5e4f082f2c133becd4338661ac16 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 19:18:05 -0700
Subject: [PATCH 046/111] opt_expr to trim A port of $shiftx if Y_WIDTH == 1

---
 passes/opt/opt_expr.cc | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 858b3560c..b56ce252f 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -745,6 +745,23 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
+		if (cell->type == ID($shiftx) && cell->getPort(ID::Y).size() == 1) {
+			SigSpec sig_a = assign_map(cell->getPort(ID::A));
+			int width;
+			for (width = GetSize(sig_a); width > 1; width--) {
+				if (sig_a[width-1] != State::Sx)
+					break;
+			}
+
+			if (width < GetSize(sig_a)) {
+				sig_a.remove(width, GetSize(sig_a)-width);
+				cell->setPort(ID::A, sig_a);
+				cell->setParam(ID(A_WIDTH), width);
+				did_something = true;
+				goto next_cell;
+			}
+		}
+
 		if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID::Y).size() == 1 &&
 				invert_map.count(assign_map(cell->getPort(ID::A))) != 0) {
 			cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str());

From bb1a8a019030022e8e5ad794691497c725ec86b2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 21:58:20 -0700
Subject: [PATCH 047/111] Add test

---
 tests/opt/opt_expr.ys | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index f0306efa1..4affc1ac8 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -221,3 +221,17 @@ check
 equiv_opt opt_expr -fine
 design -load postopt
 select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_shiftx(input [2:0] a, input [1:0] b, output y);
+    \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shiftx (.A({1'bx,a}), .B(b), .Y(y));
+endmodule
+EOT
+check
+
+equiv_opt opt_expr
+design -load postopt
+select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i

From d0ffe7544cd3c808857f3a99bbf330de61c618f2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 08:05:01 -0700
Subject: [PATCH 048/111] Canonical form

---
 passes/opt/opt_expr.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index b56ce252f..7fdfa82bd 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -369,7 +369,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	for (auto cell : module->cells())
 		if (design->selected(module, cell) && cell->type[0] == '$') {
 			if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
-					cell->getPort(ID::A).size() == 1 && cell->getPort(ID::Y).size() == 1)
+					GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
 				invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
 			if (cell->type.in(ID($mux), ID($_MUX_)) &&
 					cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))
@@ -740,12 +740,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($lt), ID($le), ID($ge), ID($gt)))
 					replace_cell(assign_map, module, cell, "x-bit in input", ID::Y, RTLIL::State::Sx);
 				else
-					replace_cell(assign_map, module, cell, "x-bit in input", ID::Y, RTLIL::SigSpec(RTLIL::State::Sx, cell->getPort(ID::Y).size()));
+					replace_cell(assign_map, module, cell, "x-bit in input", ID::Y, RTLIL::SigSpec(RTLIL::State::Sx, GetSize(cell->getPort(ID::Y))));
 				goto next_cell;
 			}
 		}
 
-		if (cell->type == ID($shiftx) && cell->getPort(ID::Y).size() == 1) {
+		if (cell->type == ID($shiftx) && GetSize(cell->getPort(ID::Y)) == 1) {
 			SigSpec sig_a = assign_map(cell->getPort(ID::A));
 			int width;
 			for (width = GetSize(sig_a); width > 1; width--) {
@@ -762,7 +762,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID::Y).size() == 1 &&
+		if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && GetSize(cell->getPort(ID::Y)) == 1 &&
 				invert_map.count(assign_map(cell->getPort(ID::A))) != 0) {
 			cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str());
 			replace_cell(assign_map, module, cell, "double_invert", ID::Y, invert_map.at(assign_map(cell->getPort(ID::A))));
@@ -1159,7 +1159,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 		if (mux_undef && cell->type.in(ID($mux), ID($pmux))) {
 			RTLIL::SigSpec new_a, new_b, new_s;
-			int width = cell->getPort(ID::A).size();
+			int width = GetSize(cell->getPort(ID::A));
 			if ((cell->getPort(ID::A).is_fully_undef() && cell->getPort(ID::B).is_fully_undef()) ||
 					cell->getPort(ID(S)).is_fully_undef()) {
 				cover_list("opt.opt_expr.mux_undef", "$mux", "$pmux", cell->type.str());

From 9e31f01b343a9b246430419e81da647e75bd1626 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 08:06:24 -0700
Subject: [PATCH 049/111] Add cover()

---
 passes/opt/opt_expr.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 7fdfa82bd..aca15e5f2 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -754,6 +754,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 
 			if (width < GetSize(sig_a)) {
+				cover("opt.opt_expr.trim_shiftx");
 				sig_a.remove(width, GetSize(sig_a)-width);
 				cell->setPort(ID::A, sig_a);
 				cell->setParam(ID(A_WIDTH), width);

From 379f33af5489850ef8e2e58ef12ff5b22da87711 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 08:22:23 -0700
Subject: [PATCH 050/111] Handle $shift and Y_WIDTH > 1 as per @cliffordwolf

---
 passes/opt/opt_expr.cc | 12 ++++++++----
 tests/opt/opt_expr.ys  | 44 +++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 51 insertions(+), 5 deletions(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index aca15e5f2..c4da613ab 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -745,16 +745,20 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if (cell->type == ID($shiftx) && GetSize(cell->getPort(ID::Y)) == 1) {
+		if (cell->type.in(ID($shiftx), ID($shift))) {
 			SigSpec sig_a = assign_map(cell->getPort(ID::A));
 			int width;
+			bool trim_x = true;
+			bool trim_0 = cell->type == ID($shift);
 			for (width = GetSize(sig_a); width > 1; width--) {
-				if (sig_a[width-1] != State::Sx)
-					break;
+				if ((trim_x && sig_a[width-1] == State::Sx) ||
+					(trim_0 && sig_a[width-1] == State::S0))
+					continue;
+				break;
 			}
 
 			if (width < GetSize(sig_a)) {
-				cover("opt.opt_expr.trim_shiftx");
+				cover_list("opt.opt_expr.xbit", "$shiftx", "$shift", cell->type.str());
 				sig_a.remove(width, GetSize(sig_a)-width);
 				cell->setPort(ID::A, sig_a);
 				cell->setParam(ID(A_WIDTH), width);
diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index 4affc1ac8..02be20a62 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -226,7 +226,7 @@ select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 
 design -reset
 read_verilog -icells <<EOT
-module opt_expr_shiftx(input [2:0] a, input [1:0] b, output y);
+module opt_expr_shiftx_1bit(input [2:0] a, input [1:0] b, output y);
     \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shiftx (.A({1'bx,a}), .B(b), .Y(y));
 endmodule
 EOT
@@ -235,3 +235,45 @@ check
 equiv_opt opt_expr
 design -load postopt
 select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_shiftx_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
+    \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shiftx (.A({4'bxx00,a}), .B(b), .Y(y));
+endmodule
+EOT
+check
+
+equiv_opt opt_expr
+design -load postopt
+select -assert-count 1 t:$shiftx r:A_WIDTH=12 %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_shift_1bit(input [2:0] a, input [1:0] b, output y);
+    \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shift (.A({1'b0,a}), .B(b), .Y(y));
+endmodule
+EOT
+check
+
+equiv_opt opt_expr
+design -load postopt
+select -assert-count 1 t:$shift r:A_WIDTH=3 %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_shift_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
+    \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
+endmodule
+EOT
+check
+
+equiv_opt opt_expr
+design -load postopt
+select -assert-count 1 t:$shift r:A_WIDTH=10 %i

From 6f971470f83b8e4ed29232be4b6cb5da89d50dc0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 08:37:27 -0700
Subject: [PATCH 051/111] Respect opt_expr -keepdc as per @cliffordwolf

---
 passes/opt/opt_expr.cc |  2 +-
 tests/opt/opt_expr.ys  | 14 ++++++++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index c4da613ab..73f48317a 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -748,7 +748,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		if (cell->type.in(ID($shiftx), ID($shift))) {
 			SigSpec sig_a = assign_map(cell->getPort(ID::A));
 			int width;
-			bool trim_x = true;
+			bool trim_x = cell->type == ID($shiftx) || !keepdc;
 			bool trim_0 = cell->type == ID($shift);
 			for (width = GetSize(sig_a); width > 1; width--) {
 				if ((trim_x && sig_a[width-1] == State::Sx) ||
diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index 02be20a62..ecc2c8da8 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -277,3 +277,17 @@ check
 equiv_opt opt_expr
 design -load postopt
 select -assert-count 1 t:$shift r:A_WIDTH=10 %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_shift_3bit_keepdc(input [9:0] a, input [3:0] b, output [2:0] y);
+    \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
+endmodule
+EOT
+check
+
+equiv_opt opt_expr -keepdc
+design -load postopt
+select -assert-count 1 t:$shift r:A_WIDTH=13 %i

From d0322e958427bd75d9c842c01b5aacb89df33cb2 Mon Sep 17 00:00:00 2001
From: Chris Shucksmith <chris@bitmex.com>
Date: Thu, 22 Aug 2019 16:37:40 +0100
Subject: [PATCH 052/111] require tcl-tk in Brewfile

---
 Brewfile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Brewfile b/Brewfile
index 0c58ce161..4ffe50e86 100644
--- a/Brewfile
+++ b/Brewfile
@@ -6,3 +6,4 @@ brew "git"
 brew "graphviz"
 brew "pkg-config"
 brew "python3"
+brew "tcl-tk"

From 9245f0d3f564644290b6650b3f8f642789062e9e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 08:43:44 -0700
Subject: [PATCH 053/111] Copy-paste typo

---
 passes/opt/opt_expr.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 73f48317a..00d7d6063 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -758,7 +758,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 
 			if (width < GetSize(sig_a)) {
-				cover_list("opt.opt_expr.xbit", "$shiftx", "$shift", cell->type.str());
+				cover_list("opt.opt_expr.trim", "$shiftx", "$shift", cell->type.str());
 				sig_a.remove(width, GetSize(sig_a)-width);
 				cell->setPort(ID::A, sig_a);
 				cell->setParam(ID(A_WIDTH), width);

From 4c449caf9bb7a855b8e61cb96f99f59141ea6ef5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 22 Aug 2019 18:06:36 +0200
Subject: [PATCH 054/111] Fix missing newline at end of file

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/efinix/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc
index f1ce58276..5013f7fc1 100644
--- a/techlibs/efinix/Makefile.inc
+++ b/techlibs/efinix/Makefile.inc
@@ -7,4 +7,4 @@ $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
 $(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v))
-$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt))
\ No newline at end of file
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt))

From 151db528e44fd12f3c31561df3bb37c12dca48ad Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 22 Aug 2019 18:09:37 +0200
Subject: [PATCH 055/111] Fix missing newline at end of file

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/anlogic/arith_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v
index d783b0212..1186543da 100644
--- a/techlibs/anlogic/arith_map.v
+++ b/techlibs/anlogic/arith_map.v
@@ -81,4 +81,4 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
 
    /* End implementation */
    assign X = AA ^ BB;
-endmodule
\ No newline at end of file
+endmodule

From e9f3eb97607bc49b6bb77229f1fad9796aea1483 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 22 Aug 2019 18:43:16 +0200
Subject: [PATCH 056/111] Bump year in copyright notice

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 COPYING         | 2 +-
 README.md       | 2 +-
 kernel/yosys.cc | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/COPYING b/COPYING
index a121cdfe9..0839088c3 100644
--- a/COPYING
+++ b/COPYING
@@ -1,4 +1,4 @@
-Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>
+Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>
 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
diff --git a/README.md b/README.md
index 56f428548..a31bd6c37 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 ```
 yosys -- Yosys Open SYnthesis Suite
 
-Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>
+Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>
 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 747f2d739..5018a4888 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -129,7 +129,7 @@ void yosys_banner()
 	log(" |                                                                            |\n");
 	log(" |  yosys -- Yosys Open SYnthesis Suite                                       |\n");
 	log(" |                                                                            |\n");
-	log(" |  Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>           |\n");
+	log(" |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |\n");
 	log(" |                                                                            |\n");
 	log(" |  Permission to use, copy, modify, and/or distribute this software for any  |\n");
 	log(" |  purpose with or without fee is hereby granted, provided that the above    |\n");

From 5e0f6c9ae58a91e7ef631ee67dd494e22fd784f0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 22 Aug 2019 18:43:16 +0200
Subject: [PATCH 057/111] Bump year in copyright notice

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 COPYING         | 2 +-
 README.md       | 2 +-
 kernel/yosys.cc | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/COPYING b/COPYING
index a121cdfe9..0839088c3 100644
--- a/COPYING
+++ b/COPYING
@@ -1,4 +1,4 @@
-Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>
+Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>
 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
diff --git a/README.md b/README.md
index 42f972c8e..83167bfee 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 ```
 yosys -- Yosys Open SYnthesis Suite
 
-Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>
+Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>
 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 94d6d675f..69a141768 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -129,7 +129,7 @@ void yosys_banner()
 	log(" |                                                                            |\n");
 	log(" |  yosys -- Yosys Open SYnthesis Suite                                       |\n");
 	log(" |                                                                            |\n");
-	log(" |  Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>           |\n");
+	log(" |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |\n");
 	log(" |                                                                            |\n");
 	log(" |  Permission to use, copy, modify, and/or distribute this software for any  |\n");
 	log(" |  purpose with or without fee is hereby granted, provided that the above    |\n");

From e5dac8096d92f526476f2d0b02def2298e6f5bbf Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 22 Aug 2019 20:43:52 +0200
Subject: [PATCH 058/111] do not require boost if pyosys is not used

---
 Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Makefile b/Makefile
index 666223076..a742f2e50 100644
--- a/Makefile
+++ b/Makefile
@@ -91,8 +91,10 @@ PLUGIN_LDFLAGS += -undefined dynamic_lookup
 ifneq ($(shell which brew),)
 BREW_PREFIX := $(shell brew --prefix)/opt
 $(info $$BREW_PREFIX is [${BREW_PREFIX}])
+ifeq ($(ENABLE_PYOSYS),1)
 CXXFLAGS += -I$(BREW_PREFIX)/boost/include/boost
 LDFLAGS += -L$(BREW_PREFIX)/boost/lib
+endif
 CXXFLAGS += -I$(BREW_PREFIX)/readline/include
 LDFLAGS += -L$(BREW_PREFIX)/readline/lib
 PKG_CONFIG_PATH := $(BREW_PREFIX)/libffi/lib/pkgconfig:$(PKG_CONFIG_PATH)

From 68e673d687e18ec8e18555cda0a0d83ca2afc84d Mon Sep 17 00:00:00 2001
From: Chris Shucksmith <chris@bitmex.com>
Date: Thu, 22 Aug 2019 16:37:40 +0100
Subject: [PATCH 059/111] require tcl-tk in Brewfile

---
 Brewfile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Brewfile b/Brewfile
index 0c58ce161..4ffe50e86 100644
--- a/Brewfile
+++ b/Brewfile
@@ -6,3 +6,4 @@ brew "git"
 brew "graphviz"
 brew "pkg-config"
 brew "python3"
+brew "tcl-tk"

From 7fafaa896dc16e83347ab33cc649da1f8e8033b7 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 22 Aug 2019 20:43:52 +0200
Subject: [PATCH 060/111] do not require boost if pyosys is not used

---
 Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Makefile b/Makefile
index 89155fae8..21f1c5f46 100644
--- a/Makefile
+++ b/Makefile
@@ -90,8 +90,10 @@ PLUGIN_LDFLAGS += -undefined dynamic_lookup
 ifneq ($(shell which brew),)
 BREW_PREFIX := $(shell brew --prefix)/opt
 $(info $$BREW_PREFIX is [${BREW_PREFIX}])
+ifeq ($(ENABLE_PYOSYS),1)
 CXXFLAGS += -I$(BREW_PREFIX)/boost/include/boost
 LDFLAGS += -L$(BREW_PREFIX)/boost/lib
+endif
 CXXFLAGS += -I$(BREW_PREFIX)/readline/include
 LDFLAGS += -L$(BREW_PREFIX)/readline/lib
 PKG_CONFIG_PATH := $(BREW_PREFIX)/libffi/lib/pkgconfig:$(PKG_CONFIG_PATH)

From c50d68653d093a8daa47f589836e6178be82b54f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 14:20:03 -0700
Subject: [PATCH 061/111] Spelling

---
 passes/equiv/equiv_make.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index dbd8682e6..4855ce29e 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -532,10 +532,10 @@ struct EquivMakePass : public Pass {
 			log_cmd_error("Equiv module %s already exists.\n", args[argidx+2].c_str());
 
 		if (worker.gold_mod->has_memories() || worker.gold_mod->has_processes())
-			log_cmd_error("Gold module contains memories or procresses. Run 'memory' or 'proc' respectively.\n");
+			log_cmd_error("Gold module contains memories or processes. Run 'memory' or 'proc' respectively.\n");
 
 		if (worker.gate_mod->has_memories() || worker.gate_mod->has_processes())
-			log_cmd_error("Gate module contains memories or procresses. Run 'memory' or 'proc' respectively.\n");
+			log_cmd_error("Gate module contains memories or processes. Run 'memory' or 'proc' respectively.\n");
 
 		worker.read_blacklists();
 		worker.read_encfiles();

From 51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 16:42:19 -0700
Subject: [PATCH 062/111] In sat: 'x' in init attr should not override constant

---
 passes/sat/sat.cc    | 2 ++
 tests/sat/initval.v  | 4 ++++
 tests/sat/initval.ys | 2 +-
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index dd56d8c71..bcc690fa3 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -268,6 +268,8 @@ struct SatHelper
 				RTLIL::SigSpec removed_bits;
 				for (int i = 0; i < lhs.size(); i++) {
 					RTLIL::SigSpec bit = lhs.extract(i, 1);
+					if (bit.is_fully_const() && rhs[i] == State::Sx)
+						rhs[i] = bit;
 					if (!satgen.initial_state.check_all(bit)) {
 						removed_bits.append(bit);
 						lhs.remove(i, 1);
diff --git a/tests/sat/initval.v b/tests/sat/initval.v
index 5b661f8d6..d46ccae48 100644
--- a/tests/sat/initval.v
+++ b/tests/sat/initval.v
@@ -1,6 +1,7 @@
 module test(input clk, input [3:0] bar, output [3:0] foo);
   reg [3:0] foo = 0;
   reg [3:0] last_bar = 0;
+  reg [3:0] asdf = 4'b1xxx;
 
   always @*
     foo[1:0] <= bar[1:0];
@@ -11,5 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
   always @(posedge clk)
     last_bar <= bar;
 
+  always @*
+    asdf[2:0] <= 3'b111;
+
   assert property (foo == {last_bar[3:2], bar[1:0]});
 endmodule
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 2079d2f34..3d88aa971 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -1,4 +1,4 @@
 read_verilog -sv initval.v
-proc;;
+proc;
 
 sat -seq 10 -prove-asserts

From fe1b2337fd7950e1d563be5b8ccbaa81688261e4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 16:57:59 -0700
Subject: [PATCH 063/111] Do not propagate mem2reg attribute through to result

---
 frontends/ast/simplify.cc | 3 ++-
 tests/various/mem2reg.ys  | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 8493aa513..86dd80c65 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -151,7 +151,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 					reg->is_reg = true;
 					reg->is_signed = node->is_signed;
 					for (auto &it : node->attributes)
-						reg->attributes.emplace(it.first, it.second->clone());
+						if (it.first != ID(mem2reg))
+							reg->attributes.emplace(it.first, it.second->clone());
 					reg->filename = node->filename;
 					reg->linenum = node->linenum;
 					children.push_back(reg);
diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys
index 00389c700..85d6267c5 100644
--- a/tests/various/mem2reg.ys
+++ b/tests/various/mem2reg.ys
@@ -11,3 +11,4 @@ proc
 cd top
 select -assert-count 1 m:data1 a:src=<<EOT:4 %i
 select -assert-count 2 w:data2[*] a:src=<<EOT:5 %i
+select -assert-none a:mem2reg

From c618ae43b9e8121690c2842622074a95a12c9fe5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 23 Aug 2019 10:37:50 +0200
Subject: [PATCH 064/111] Make macOS depenency clear

---
 README.md | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index a31bd6c37..606c4942e 100644
--- a/README.md
+++ b/README.md
@@ -69,11 +69,14 @@ prerequisites for building yosys:
 		graphviz xdot pkg-config python3 libboost-system-dev \
 		libboost-python-dev libboost-filesystem-dev zlib1g-dev
 
-Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
+Similarily, on Mac OS X Homebrew can be used to install dependencies:
 
 	$ brew tap Homebrew/bundle && brew bundle
+
+or MacPorts:
+
 	$ sudo port install bison flex readline gawk libffi \
-		git graphviz pkgconfig python36 boost zlib
+		git graphviz pkgconfig python36 boost zlib tcl
 
 On FreeBSD use the following command to install all prerequisites:
 

From adb81ba3861d66a94f237fd29a67b8978980cd37 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 23 Aug 2019 16:15:50 +0200
Subject: [PATCH 065/111] Add pmgen slices and choices

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 CHANGELOG                   |   1 +
 passes/pmgen/README.md      |  48 ++++++++++++++-
 passes/pmgen/pmgen.py       | 116 +++++++++++++++++++++++++++++-------
 passes/pmgen/test_pmgen.cc  |  53 +++++++++++++++-
 passes/pmgen/test_pmgen.pmg |  87 ++++++++++++++++++++++++++-
 5 files changed, 277 insertions(+), 28 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index ca42df71e..dd94c76ed 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -27,6 +27,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "opt_share" pass, run as part of "opt -full"
     - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
     - Removed "ice40_unlut"
+    - Improvements in pmgen: slices, choices, define, generate
 
 Yosys 0.8 .. Yosys 0.8-dev
 --------------------------
diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md
index 5f6a8ab1b..27ed77091 100644
--- a/passes/pmgen/README.md
+++ b/passes/pmgen/README.md
@@ -178,6 +178,45 @@ evaluates to `false`.
 The `semioptional` statement marks matches that must match if at least one
 matching cell exists, but if no matching cell exists it is set to `nullptr`.
 
+Slices and choices
+------------------
+
+Cell matches can contain "slices" and "choices". Slices can be used to
+create matches for different sections of a cell. For example:
+
+    state <int> pmux_slice
+
+    match pmux
+        select pmux->type == $pmux
+        slice idx GetSize(port(pmux, \S))
+        index <SigBit> port(pmux, \S)[idx] === port(eq, \Y)
+	set pmux_slice idx
+    endmatch
+
+The first argument to `slice` is the local variable name used to identify the
+slice. The second argument is the number of slices that should be created for
+this cell. The `set` statement can be used to copy that index indo a state
+variable so that later matches and/or code blocks can refer to it.
+
+A similar mechanism is "choices", where a list of options is given as
+second argument, and the matcher will iterate over those options:
+
+    state <SigSpec> foo bar
+    state <IdString> eq_ab eq_ba
+
+    match eq
+        select eq->type == $eq
+        choice <IdString> AB {\A, \B}
+        define <IdString> BA (AB == \A ? \B : \A)
+        index <SigSpec> port(eq, AB) === foo
+        index <SigSpec> port(eq, BA) === bar
+        set eq_ab AB
+        set eq_ba BA
+    generate
+
+Notice how `define` can be used to define additional local variables similar
+to the loop variables defined by `slice` and `choice`.
+
 Additional code
 ---------------
 
@@ -326,7 +365,7 @@ test-case generation. For example:
 
     match mul
         ...
-    generate 10
+    generate 10 0
         SigSpec Y = port(ff, \D);
         SigSpec A = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
         SigSpec B = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
@@ -335,8 +374,11 @@ test-case generation. For example:
 
 The expression `rng(n)` returns a non-negative integer less than `n`.
 
-The argument to `generate` is the chance of this generate block being executed
-when the match block did not match anything, in percent.
+The first argument to `generate` is the chance of this generate block being
+executed when the match block did not match anything, in percent.
+
+The second argument to `generate` is the chance of this generate block being
+executed when the match block did match something, in percent.
 
 The special statement `finish` can be used within generate blocks to terminate
 the current pattern matcher run.
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index 18c3bf5a5..c2621393d 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -207,9 +207,10 @@ def process_pmgfile(f, filename):
             state_types[current_pattern][line[1]] = "Cell*";
 
             block["if"] = list()
-            block["select"] = list()
+            block["setup"] = list()
             block["index"] = list()
             block["filter"] = list()
+            block["sets"] = list()
             block["optional"] = False
             block["semioptional"] = False
 
@@ -228,7 +229,22 @@ def process_pmgfile(f, filename):
 
                 if a[0] == "select":
                     b = l.lstrip()[6:]
-                    block["select"].append(rewrite_cpp(b.strip()))
+                    block["setup"].append(("select", rewrite_cpp(b.strip())))
+                    continue
+
+                if a[0] == "slice":
+                    m = re.match(r"^\s*slice\s+(\S+)\s+(.*?)\s*$", l)
+                    block["setup"].append(("slice", m.group(1), rewrite_cpp(m.group(2))))
+                    continue
+
+                if a[0] == "choice":
+                    m = re.match(r"^\s*choice\s+<(.*?)>\s+(\S+)\s+(.*?)\s*$", l)
+                    block["setup"].append(("choice", m.group(1), m.group(2), rewrite_cpp(m.group(3))))
+                    continue
+
+                if a[0] == "define":
+                    m = re.match(r"^\s*define\s+<(.*?)>\s+(\S+)\s+(.*?)\s*$", l)
+                    block["setup"].append(("define", m.group(1), m.group(2), rewrite_cpp(m.group(3))))
                     continue
 
                 if a[0] == "index":
@@ -242,6 +258,11 @@ def process_pmgfile(f, filename):
                     block["filter"].append(rewrite_cpp(b.strip()))
                     continue
 
+                if a[0] == "set":
+                    m = re.match(r"^\s*set\s+(\S+)\s+(.*?)\s*$", l)
+                    block["sets"].append((m.group(1), rewrite_cpp(m.group(2))))
+                    continue
+
                 if a[0] == "optional":
                     block["optional"] = True
                     continue
@@ -252,14 +273,16 @@ def process_pmgfile(f, filename):
 
                 if a[0] == "generate":
                     block["genargs"] = list([int(s) for s in a[1:]])
+                    if len(block["genargs"]) == 0: block["genargs"].append(100)
+                    if len(block["genargs"]) == 1: block["genargs"].append(0)
+                    assert len(block["genargs"]) == 2
                     block["gencode"] = list()
-                    assert len(block["genargs"]) < 2
                     while True:
                         linenr += 1
                         l = f.readline()
                         assert l != ""
                         a = l.split()
-                        if a[0] == "endmatch": break
+                        if len(a) == 1 and a[0] == "endmatch": break
                         block["gencode"].append(rewrite_cpp(l.rstrip()))
                     break
 
@@ -357,8 +380,17 @@ with open(outfile, "w") as f:
             index_types = list()
             for entry in block["index"]:
                 index_types.append(entry[0])
+            value_types = ["Cell*"]
+            for entry in block["setup"]:
+                if entry[0] == "slice":
+                    value_types.append("int")
+                if entry[0] == "choice":
+                    value_types.append(entry[1])
+                if entry[0] == "define":
+                    value_types.append(entry[1])
             print("  typedef std::tuple<{}> index_{}_key_type;".format(", ".join(index_types), index), file=f)
-            print("  dict<index_{}_key_type, vector<Cell*>> index_{};".format(index, index), file=f)
+            print("  typedef std::tuple<{}> index_{}_value_type;".format(", ".join(value_types), index), file=f)
+            print("  dict<index_{}_key_type, vector<index_{}_value_type>> index_{};".format(index, index, index), file=f)
     print("  dict<SigBit, pool<Cell*>> sigusers;", file=f)
     print("  pool<Cell*> blacklist_cells;", file=f)
     print("  pool<Cell*> autoremove_cells;", file=f)
@@ -457,12 +489,34 @@ with open(outfile, "w") as f:
         if block["type"] == "match":
             print("      do {", file=f)
             print("        Cell *{} = cell;".format(block["cell"]), file=f)
-            for expr in block["select"]:
-                print("        if (!({})) break;".format(expr), file=f)
+            print("        index_{}_value_type value;".format(index), file=f)
+            print("        std::get<0>(value) = cell;", file=f)
+            loopcnt = 0
+            valueidx = 1
+            for item in block["setup"]:
+                if item[0] == "select":
+                    print("        if (!({})) continue;".format(item[1]), file=f)
+                if item[0] == "slice":
+                    print("        int &{} = std::get<{}>(value);".format(item[1], valueidx), file=f)
+                    print("        for ({} = 0; {} < {}; {}++) {{".format(item[1], item[1], item[2], item[1]), file=f)
+                    valueidx += 1
+                    loopcnt += 1
+                if item[0] == "choice":
+                    print("        vector<{}> _pmg_choices_{} = {};".format(item[1], item[2], item[3]), file=f)
+                    print("        for (const {} &{} : _pmg_choices_{}) {{".format(item[1], item[2], item[2]), file=f)
+                    print("        std::get<{}>(value) = {};".format(valueidx, item[2]), file=f)
+                    valueidx += 1
+                    loopcnt += 1
+                if item[0] == "define":
+                    print("        {} &{} = std::get<{}>(value);".format(item[1], item[2], valueidx), file=f)
+                    print("        {} = {};".format(item[2], item[3]), file=f)
+                    valueidx += 1
             print("        index_{}_key_type key;".format(index), file=f)
             for field, entry in enumerate(block["index"]):
                 print("        std::get<{}>(key) = {};".format(field, entry[1]), file=f)
-            print("        index_{}[key].push_back(cell);".format(index), file=f)
+            print("        index_{}[key].push_back(value);".format(index), file=f)
+            for i in range(loopcnt):
+                print("        }", file=f)
             print("      } while (0);", file=f)
 
     print("    }", file=f)
@@ -535,6 +589,8 @@ with open(outfile, "w") as f:
                     const_st.add(s)
             elif blocks[i]["type"] == "match":
                 const_st.add(blocks[i]["cell"])
+                for item in blocks[i]["sets"]:
+                    const_st.add(item[0])
             else:
                 assert False
 
@@ -548,6 +604,10 @@ with open(outfile, "w") as f:
             s = block["cell"]
             assert s not in const_st
             nonconst_st.add(s)
+            for item in block["sets"]:
+                if item[0] in const_st:
+                    const_st.remove(item[0])
+                nonconst_st.add(item[0])
         else:
             assert False
 
@@ -570,7 +630,7 @@ with open(outfile, "w") as f:
             print("", file=f)
             for s in sorted(restore_st):
                 t = state_types[current_pattern][s]
-                print("    {} backup_{} = {};".format(t, s, s), file=f)
+                print("    {} _pmg_backup_{} = {};".format(t, s, s), file=f)
 
         if block["type"] == "code":
             print("", file=f)
@@ -610,7 +670,7 @@ with open(outfile, "w") as f:
                 print("", file=f)
                 for s in sorted(restore_st):
                     t = state_types[current_pattern][s]
-                    print("    {} = backup_{};".format(s, s), file=f)
+                    print("    {} = _pmg_backup_{};".format(s, s), file=f)
                 for s in sorted(nonconst_st):
                     if s not in restore_st:
                         t = state_types[current_pattern][s]
@@ -622,7 +682,7 @@ with open(outfile, "w") as f:
         elif block["type"] == "match":
             assert len(restore_st) == 0
 
-            print("    Cell* backup_{} = {};".format(block["cell"], block["cell"]), file=f)
+            print("    Cell* _pmg_backup_{} = {};".format(block["cell"], block["cell"]), file=f)
 
             if len(block["if"]):
                 for expr in block["if"]:
@@ -630,7 +690,7 @@ with open(outfile, "w") as f:
                     print("    if (!({})) {{".format(expr), file=f)
                     print("      {} = nullptr;".format(block["cell"]), file=f)
                     print("      block_{}(recursion+1);".format(index+1), file=f)
-                    print("      {} = backup_{};".format(block["cell"], block["cell"]), file=f)
+                    print("      {} = _pmg_backup_{};".format(block["cell"], block["cell"]), file=f)
                     print("      return;", file=f)
                     print("    }", file=f)
 
@@ -645,21 +705,37 @@ with open(outfile, "w") as f:
 
             print("", file=f)
             print("    if (cells_ptr != index_{}.end()) {{".format(index), file=f)
-            print("      const vector<Cell*> &cells = cells_ptr->second;".format(index), file=f)
-            print("      for (int idx = 0; idx < GetSize(cells); idx++) {", file=f)
-            print("        {} = cells[idx];".format(block["cell"]), file=f)
+            print("      const vector<index_{}_value_type> &cells = cells_ptr->second;".format(index), file=f)
+            print("      for (int _pmg_idx = 0; _pmg_idx < GetSize(cells); _pmg_idx++) {", file=f)
+            print("        {} = std::get<0>(cells[_pmg_idx]);".format(block["cell"]), file=f)
+            valueidx = 1
+            for item in block["setup"]:
+                if item[0] == "slice":
+                    print("        const int &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], valueidx), file=f)
+                    valueidx += 1
+                if item[0] == "choice":
+                    print("        const {} &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
+                    valueidx += 1
+                if item[0] == "define":
+                    print("        const {} &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
+                    valueidx += 1
             print("        if (blacklist_cells.count({})) continue;".format(block["cell"]), file=f)
             for expr in block["filter"]:
                 print("        if (!({})) continue;".format(expr), file=f)
             if block["semioptional"] or block["genargs"] is not None:
                 print("        found_any_match = true;", file=f)
-            print("        auto rollback_ptr = rollback_cache.insert(make_pair(cells[idx], recursion));", file=f)
+            for item in block["sets"]:
+                print("        auto _pmg_backup_{} = {};".format(item[0], item[0]), file=f)
+                print("        {} = {};".format(item[0], item[1]), file=f)
+            print("        auto rollback_ptr = rollback_cache.insert(make_pair(std::get<0>(cells[_pmg_idx]), recursion));", file=f)
             print("        block_{}(recursion+1);".format(index+1), file=f)
+            for item in block["sets"]:
+                print("        {} = _pmg_backup_{};".format(item[0], item[0]), file=f)
             print("        if (rollback_ptr.second)", file=f)
             print("          rollback_cache.erase(rollback_ptr.first);", file=f)
             print("        if (rollback) {", file=f)
             print("          if (rollback != recursion) {{".format(index+1), file=f)
-            print("            {} = backup_{};".format(block["cell"], block["cell"]), file=f)
+            print("            {} = _pmg_backup_{};".format(block["cell"], block["cell"]), file=f)
             print("            return;", file=f)
             print("          }", file=f)
             print("          rollback = 0;", file=f)
@@ -676,13 +752,11 @@ with open(outfile, "w") as f:
             if block["semioptional"]:
                 print("    if (!found_any_match) block_{}(recursion+1);".format(index+1), file=f)
 
-            print("    {} = backup_{};".format(block["cell"], block["cell"]), file=f)
+            print("    {} = _pmg_backup_{};".format(block["cell"], block["cell"]), file=f)
 
             if block["genargs"] is not None:
                 print("#define finish do { rollback = -1; return; } while(0)", file=f)
-                print("    if (generate_mode && !found_any_match) {", file=f)
-                if len(block["genargs"]) == 1:
-                    print("    if (rng(100) >= {}) return;".format(block["genargs"][0]), file=f)
+                print("    if (generate_mode && rng(100) < (found_any_match ? {} : {})) {{".format(block["genargs"][1], block["genargs"][0]), file=f)
                 for line in block["gencode"]:
                     print("      " + line, file=f)
                 print("    }", file=f)
diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc
index 9f42a95d0..0ad769dfd 100644
--- a/passes/pmgen/test_pmgen.cc
+++ b/passes/pmgen/test_pmgen.cc
@@ -99,6 +99,24 @@ void reduce_tree(test_pmgen_pm &pm)
 	log("    -> %s (%s)\n", log_id(c), log_id(c->type));
 }
 
+void opt_eqpmux(test_pmgen_pm &pm)
+{
+	auto &st = pm.st_eqpmux;
+
+	SigSpec Y = st.pmux->getPort(ID::Y);
+	int width = GetSize(Y);
+
+	SigSpec EQ = st.pmux->getPort(ID::B).extract(st.pmux_slice_eq*width, width);
+	SigSpec NE = st.pmux->getPort(ID::B).extract(st.pmux_slice_ne*width, width);
+
+	log("Found eqpmux circuit driving %s (eq=%s, ne=%s, pmux=%s).\n",
+			log_signal(Y), log_id(st.eq), log_id(st.ne), log_id(st.pmux));
+
+	pm.autoremove(st.pmux);
+	Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(ID::Y), Y);
+	log("    -> %s (%s)\n", log_id(c), log_id(c->type));
+}
+
 #define GENERATE_PATTERN(pmclass, pattern) \
 	generate_pattern<pmclass>([](pmclass &pm, std::function<void()> f){ return pm.run_ ## pattern(f); }, #pmclass, #pattern, design)
 
@@ -149,16 +167,17 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
 	log("Generating \"%s\" patterns for pattern matcher \"%s\".\n", pattern, pmclass);
 
 	int modcnt = 0;
+	int maxmodcnt = 100;
 	int maxsubcnt = 4;
 	int timeout = 0;
 	vector<Module*> mods;
 
-	while (modcnt < 100)
+	while (modcnt < maxmodcnt)
 	{
 		int submodcnt = 0, itercnt = 0, cellcnt = 0;
 		Module *mod = design->addModule(NEW_ID);
 
-		while (modcnt < 100 && submodcnt < maxsubcnt && itercnt++ < 1000)
+		while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000)
 		{
 			if (timeout++ > 10000)
 				log_error("pmgen generator is stuck: 10000 iterations an no matching module generated.\n");
@@ -232,6 +251,12 @@ struct TestPmgenPass : public Pass {
 		log("Demo for recursive pmgen patterns. Map trees of AND/OR/XOR to $reduce_*.\n");
 		log("\n");
 
+		log("\n");
+		log("    test_pmgen -eqpmux [options] [selection]\n");
+		log("\n");
+		log("Demo for recursive pmgen patterns. Optimize EQ/NE/PMUX circuits.\n");
+		log("\n");
+
 		log("\n");
 		log("    test_pmgen -generate [options] <pattern_name>\n");
 		log("\n");
@@ -277,6 +302,25 @@ struct TestPmgenPass : public Pass {
 			test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_tree);
 	}
 
+	void execute_eqpmux(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header(design, "Executing TEST_PMGEN pass (-eqpmux).\n");
+
+		size_t argidx;
+		for (argidx = 2; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-singleton") {
+			// 	singleton_mode = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+			test_pmgen_pm(module, module->selected_cells()).run_eqpmux(opt_eqpmux);
+	}
+
 	void execute_generate(std::vector<std::string> args, RTLIL::Design *design)
 	{
 		log_header(design, "Executing TEST_PMGEN pass (-generate).\n");
@@ -299,6 +343,9 @@ struct TestPmgenPass : public Pass {
 		if (pattern == "reduce")
 			return GENERATE_PATTERN(test_pmgen_pm, reduce);
 
+		if (pattern == "eqpmux")
+			return GENERATE_PATTERN(test_pmgen_pm, eqpmux);
+
 		if (pattern == "ice40_dsp")
 			return GENERATE_PATTERN(ice40_dsp_pm, ice40_dsp);
 
@@ -319,6 +366,8 @@ struct TestPmgenPass : public Pass {
 				return execute_reduce_chain(args, design);
 			if (args[1] == "-reduce_tree")
 				return execute_reduce_tree(args, design);
+			if (args[1] == "-eqpmux")
+				return execute_eqpmux(args, design);
 			if (args[1] == "-generate")
 				return execute_generate(args, design);
 		}
diff --git a/passes/pmgen/test_pmgen.pmg b/passes/pmgen/test_pmgen.pmg
index 211477a62..287ed97d8 100644
--- a/passes/pmgen/test_pmgen.pmg
+++ b/passes/pmgen/test_pmgen.pmg
@@ -60,8 +60,8 @@ code portname
 endcode
 
 match next
-	select nusers(port(next, \Y)) == 2
 	select next->type.in($_AND_, $_OR_, $_XOR_)
+	select nusers(port(next, \Y)) == 2
 	index <IdString> next->type === first->type
 	index <SigSpec> port(next, \Y) === port(first, portname)
 endmatch
@@ -77,8 +77,8 @@ arg first
 
 match next
 	semioptional
-	select nusers(port(next, \Y)) == 2
 	select next->type.in($_AND_, $_OR_, $_XOR_)
+	select nusers(port(next, \Y)) == 2
 	index <IdString> next->type === chain.back().first->type
 	index <SigSpec> port(next, \Y) === port(chain.back().first, chain.back().second)
 generate 10
@@ -104,3 +104,86 @@ finally
 	if (next)
 		chain.pop_back();
 endcode
+
+// ==================================================================
+
+pattern eqpmux
+
+state <bool> eq_ne_signed
+state <SigSpec> eq_inA eq_inB
+state <int> pmux_slice_eq pmux_slice_ne
+
+match eq
+	select eq->type == $eq
+	choice <IdString> AB {\A, \B}
+	define <IdString> BA AB == \A ? \B : \A
+	set eq_inA port(eq, \A)
+	set eq_inB port(eq, \B)
+	set eq_ne_signed param(eq, \A_SIGNED).as_bool()
+generate 100 10
+	SigSpec A = module->addWire(NEW_ID, rng(7)+1);
+	SigSpec B = module->addWire(NEW_ID, rng(7)+1);
+	SigSpec Y = module->addWire(NEW_ID);
+	module->addEq(NEW_ID, A, B, Y, rng(2));
+endmatch
+
+match pmux
+	select pmux->type == $pmux
+	slice idx GetSize(port(pmux, \S))
+	index <SigBit> port(pmux, \S)[idx] === port(eq, \Y)
+	set pmux_slice_eq idx
+generate 100 10
+	int width = rng(7) + 1;
+	int numsel = rng(4) + 1;
+	int idx = rng(numsel);
+
+	SigSpec A = module->addWire(NEW_ID, width);
+	SigSpec Y = module->addWire(NEW_ID, width);
+
+	SigSpec B, S;
+	for (int i = 0; i < numsel; i++) {
+		B.append(module->addWire(NEW_ID, width));
+		S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_ID));
+	}
+
+	module->addPmux(NEW_ID, A, B, S, Y);
+endmatch
+
+match ne
+	select ne->type == $ne
+	choice <IdString> AB {\A, \B}
+	define <IdString> BA (AB == \A ? \B : \A)
+	index <SigSpec> port(ne, AB) === eq_inA
+	index <SigSpec> port(ne, BA) === eq_inB
+	index <int> param(ne, \A_SIGNED).as_bool() === eq_ne_signed
+generate 100 10
+	SigSpec A = eq_inA, B = eq_inB, Y;
+	if (rng(2)) {
+		std::swap(A, B);
+	}
+	if (rng(2)) {
+		for (auto bit : port(pmux, \S)) {
+			if (nusers(bit) < 2)
+				Y.append(bit);
+		}
+		if (GetSize(Y))
+			Y = Y[rng(GetSize(Y))];
+		else
+			Y = module->addWire(NEW_ID);
+	} else {
+		Y = module->addWire(NEW_ID);
+	}
+	module->addNe(NEW_ID, A, B, Y, rng(2));
+endmatch
+
+match pmux2
+	select pmux2->type == $pmux
+	slice idx GetSize(port(pmux2, \S))
+	index <Cell*> pmux2 === pmux
+	index <SigBit> port(pmux2, \S)[idx] === port(ne, \Y)
+	set pmux_slice_ne idx
+endmatch
+
+code
+	accept;
+endcode

From 55bf8f69e085caa0a3f0ccae8bf231f77aba6bbc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 23 Aug 2019 16:26:54 +0200
Subject: [PATCH 066/111] Fix port hanlding in pmgen

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/pmgen.py | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index c2621393d..573722d68 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -422,8 +422,6 @@ with open(outfile, "w") as f:
     print("  void add_siguser(const SigSpec &sig, Cell *cell) {", file=f)
     print("    for (auto bit : sigmap(sig)) {", file=f)
     print("      if (bit.wire == nullptr) continue;", file=f)
-    print("      if (sigusers.count(bit) == 0 && bit.wire->port_id)", file=f)
-    print("        sigusers[bit].insert(nullptr);", file=f)
     print("      sigusers[bit].insert(cell);", file=f)
     print("    }", file=f)
     print("  }", file=f)
@@ -478,10 +476,11 @@ with open(outfile, "w") as f:
             else:
                 print("    ud_{}.{} = {}();".format(current_pattern, s, t), file=f)
     current_pattern = None
-    print("    for (auto cell : module->cells()) {", file=f)
+    print("    for (auto port : module->ports)", file=f)
+    print("      add_siguser(module->wire(port), nullptr);", file=f)
+    print("    for (auto cell : module->cells())", file=f)
     print("      for (auto &conn : cell->connections())", file=f)
     print("        add_siguser(conn.second, cell);", file=f)
-    print("    }", file=f)
     print("    for (auto cell : cells) {", file=f)
 
     for index in range(len(blocks)):

From 10c41a5cf51427d96f465113decb752e501e926e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 09:11:04 -0700
Subject: [PATCH 067/111] Blocking assignment

---
 tests/sat/initval.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/sat/initval.v b/tests/sat/initval.v
index d46ccae48..fcec9dd8c 100644
--- a/tests/sat/initval.v
+++ b/tests/sat/initval.v
@@ -13,7 +13,7 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
     last_bar <= bar;
 
   always @*
-    asdf[2:0] <= 3'b111;
+    asdf[2:0] = 3'b111;
 
   assert property (foo == {last_bar[3:2], bar[1:0]});
 endmodule

From 55aa444e059fb011f0af7293845178dec2ef4a50 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 23 Aug 2019 10:37:50 +0200
Subject: [PATCH 068/111] Make macOS depenency clear

---
 README.md | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 83167bfee..5132332a5 100644
--- a/README.md
+++ b/README.md
@@ -69,11 +69,14 @@ prerequisites for building yosys:
 		graphviz xdot pkg-config python3 libboost-system-dev \
 		libboost-python-dev libboost-filesystem-dev
 
-Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
+Similarily, on Mac OS X Homebrew can be used to install dependencies:
 
 	$ brew tap Homebrew/bundle && brew bundle
+
+or MacPorts:
+
 	$ sudo port install bison flex readline gawk libffi \
-		git graphviz pkgconfig python36 boost
+		git graphviz pkgconfig python36 boost tcl
 
 On FreeBSD use the following command to install all prerequisites:
 

From 4d89c3f468b6090dceabb304b9f56f3a6a597057 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 10:03:41 -0700
Subject: [PATCH 069/111] Review comment from @cliffordwolf

---
 passes/techmap/clkbufmap.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc
index 6fac1b437..55341ead0 100644
--- a/passes/techmap/clkbufmap.cc
+++ b/passes/techmap/clkbufmap.cc
@@ -112,7 +112,8 @@ struct ClkbufmapPass : public Pass {
 		for (auto module : modules_sorted)
 		{
 			if (module->get_blackbox_attribute()) {
-				for (auto wire : module->wires()) {
+				for (auto port : module->ports) {
+					auto wire = module->wire(port);
 					if (wire->get_bool_attribute("\\clkbuf_driver"))
 						for (int i = 0; i < GetSize(wire); i++)
 							buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));

From 4c0404ae024e9595934e738a3e8f52be9c22d090 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 10:24:59 -0700
Subject: [PATCH 070/111] Mention clkbuf_inhibit can be overridden

---
 README.md | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/README.md b/README.md
index 00b631237..38ca77862 100644
--- a/README.md
+++ b/README.md
@@ -332,17 +332,18 @@ Verilog Attributes and non-standard features
   that represent module parameters or localparams (when the HDL front-end
   is run in -pwires mode).
 
-- The ``clkbuf_inhibit`` attribute can be set on a wire to prevent
-  automatic clock buffer insertion by ``clkbufmap``.
-
-- The ``clkbuf_sink`` attribute can be set on an input port of a blackbox
-  module to request clock buffer insertion by the ``clkbufmap`` pass.
-
 - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
   module to mark it as a clock buffer output, and thus prevent ``clkbufmap``
   from inserting another clock buffer on a net driven by such output.
 
-- The ``iopad_external_pin`` attribute on a blacbox module's port marks
+- The ``clkbuf_sink`` attribute can be set on an input port of a module to
+  request clock buffer insertion by the ``clkbufmap`` pass.
+
+- The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent
+  automatic clock buffer insertion by ``clkbufmap``. This behaviour can be
+  overridden by providing a custom selection to ``clkbufmap``.
+
+- The ``iopad_external_pin`` attribute on a blackbox module's port marks
   it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
   from inserting another pad cell on it.
 

From d62c10d641c5af4b1d395caa042681788df1aae4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 11:09:50 -0700
Subject: [PATCH 071/111] tests/techmap/run-test.sh to cope with *.ys

---
 tests/techmap/.gitignore  |  1 +
 tests/techmap/run-test.sh | 24 +++++++++++++++++-------
 2 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/tests/techmap/.gitignore b/tests/techmap/.gitignore
index 397b4a762..cfed22fc5 100644
--- a/tests/techmap/.gitignore
+++ b/tests/techmap/.gitignore
@@ -1 +1,2 @@
 *.log
+/*.mk
diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh
index e2fc11e52..96489ff15 100755
--- a/tests/techmap/run-test.sh
+++ b/tests/techmap/run-test.sh
@@ -1,10 +1,20 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
-for x in *_runtest.sh; do
-	echo "Running $x.."
-	if ! bash $x &> ${x%.sh}.log; then
-		tail ${x%.sh}.log
-		echo ERROR
-		exit 1
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s > ${s%.sh}.log 2>&1"
 	fi
 done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk

From 5628e2ec53c3a1d5f1828b8f522c5c09c9856b0d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 11:10:02 -0700
Subject: [PATCH 072/111] Add simple clkbufmap tests

---
 tests/techmap/clkbufmap.ys | 52 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 tests/techmap/clkbufmap.ys

diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys
new file mode 100644
index 000000000..eb8970af4
--- /dev/null
+++ b/tests/techmap/clkbufmap.ys
@@ -0,0 +1,52 @@
+read_verilog <<EOT
+module clkbuf (input i, (* clkbuf_driver *) output o); endmodule
+module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule
+module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule
+module latch (input e, d, output q); endmodule
+
+module top(input clk1, clk2, clk3, d, e, output [2:0] q);
+dff s0 (.clk(clk1), .d(d), .q(q[0]));
+dffe s1 (.c(clk2), .d(d), .e(e), .q(q[1]));
+latch s2 (.e(clk3), .d(d), .q(q[2]));
+endmodule
+EOT
+
+hierarchy -auto-top
+design -save ref
+
+# ----------------------
+
+design -load ref
+clkbufmap -buf clkbuf o:i
+select -assert-count 1 w:clk1 %a %co t:clkbuf %i
+select -assert-count 1 w:clk2 %a %co t:clkbuf %i
+select -assert-count 2 t:clkbuf
+
+# ----------------------
+
+design -load ref
+setattr -set clkbuf_inhibit 0 w:clk1
+setattr -set clkbuf_inhibit 1 w:clk2
+clkbufmap -buf clkbuf o:i
+select -assert-count 1 w:clk1 %a %co t:clkbuf %i
+select -assert-count 0 w:clk2 %a %co t:clkbuf %i
+select -assert-count 1 t:clkbuf
+
+# ----------------------
+
+design -load ref
+setattr -set buffer_type "bufg" w:clk2
+clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
+select -assert-count 1 w:clk1 %a %co t:clkbuf %i
+select -assert-count 1 w:clk2 %a %co t:clkbuf %i
+select -assert-count 2 t:clkbuf
+
+# ----------------------
+
+design -load ref
+setattr -set buffer_type "none" w:clk1
+setattr -set buffer_type "bufr" w:clk2
+clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
+select -assert-count 0 w:clk1 %a %co t:clkbuf %i
+select -assert-count 0 w:clk2 %a %co t:clkbuf %i
+select -assert-count 0 t:clkbuf

From 619f2414e587a216edb68d39ce56e25e29f0502b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 11:14:42 -0700
Subject: [PATCH 073/111] clkbufmap to only check clkbuf_inhibit if no
 selection given

---
 passes/techmap/clkbufmap.cc | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc
index 55341ead0..82b3dcdf7 100644
--- a/passes/techmap/clkbufmap.cc
+++ b/passes/techmap/clkbufmap.cc
@@ -37,11 +37,18 @@ struct ClkbufmapPass : public Pass {
 	ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { }
 	void help() YS_OVERRIDE
 	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 		log("    clkbufmap [options] [selection]\n");
 		log("\n");
-		log("Inserts global buffers between nets connected to clock inputs and their\n");
-		log("drivers.\n");
+		log("Inserts global buffers between nets connected to clock inputs and their drivers.\n");
+		log("\n");
+		log("In the absence of any selection, all wires without the 'clkbuf_inhibit'\n");
+		log("attribute will be considered for global buffer insertion.\n");
+		log("Alternatively, to consider all wires without the 'buffer_type' attribute set to\n");
+		log("'none' or 'bufr' one would specify:\n");
+		log("  'w:* a:buffer_type=none a:buffer_type=bufr %%u %%d'\n");
+		log("as the selection.\n");
 		log("\n");
 		log("    -buf <celltype> <portname_out>:<portname_in>\n");
 		log("        Specifies the cell type to use for the global buffers\n");
@@ -94,10 +101,16 @@ struct ClkbufmapPass : public Pass {
 			}
 			break;
 		}
-		extra_args(args, argidx, design);
+
+		bool select = false;
+		if (argidx < args.size()) {
+			if (args[argidx].compare(0, 1, "-") != 0)
+				select = true;
+			extra_args(args, argidx, design);
+		}
 
 		if (buf_celltype.empty())
-			log_error("The -buf option is required.");
+			log_error("The -buf option is required.\n");
 
 		// Cell type, port name, bit index.
 		pool<pair<IdString, pair<IdString, int>>> sink_ports;
@@ -158,7 +171,7 @@ struct ClkbufmapPass : public Pass {
 				// Should not happen.
 				if (wire->port_input && wire->port_output)
 					continue;
-				if (wire->get_bool_attribute("\\clkbuf_inhibit"))
+				if (!select && wire->get_bool_attribute("\\clkbuf_inhibit"))
 					continue;
 
 				pool<int> input_bits;

From a0d85393e388e3349ea501878605e47513ad1699 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 11:15:26 -0700
Subject: [PATCH 074/111] Check clkbuf_inhibit=1 is ignored for custom
 selection

---
 tests/techmap/clkbufmap.ys | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys
index eb8970af4..46ff4d694 100644
--- a/tests/techmap/clkbufmap.ys
+++ b/tests/techmap/clkbufmap.ys
@@ -35,6 +35,7 @@ select -assert-count 1 t:clkbuf
 # ----------------------
 
 design -load ref
+setattr -set clkbuf_inhibit 1 w:clk1
 setattr -set buffer_type "bufg" w:clk2
 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
 select -assert-count 1 w:clk1 %a %co t:clkbuf %i

From a270af00cc133ac03ec97cf81ed0a7146b7b225e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 11:21:44 -0700
Subject: [PATCH 075/111] Put abc_* attributes above port

---
 techlibs/ecp5/cells_sim.v   | 15 ++++++++++-----
 techlibs/ice40/cells_sim.v  |  6 ++++--
 techlibs/xilinx/cells_sim.v | 21 ++++++++++++++-------
 3 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 2fcb0369e..dc8334acb 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -17,10 +17,12 @@ endmodule
 // ---------------------------------------
 (* abc_box_id=1, lib_whitebox *)
 module CCU2C(
-	(* abc_carry *) input CIN,
+	(* abc_carry *)
+	input  CIN,
 	input  A0, B0, C0, D0, A1, B1, C1, D1,
 	output S0, S1,
-	(* abc_carry *) output COUT
+	(* abc_carry *)
+	output COUT
 );
 	parameter [15:0] INIT0 = 16'h0000;
 	parameter [15:0] INIT1 = 16'h0000;
@@ -109,9 +111,12 @@ endmodule
 // ---------------------------------------
 //(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-	(* abc_scc_break *) input [3:0] DI,
-	(* abc_scc_break *) input [3:0] WAD,
-	(* abc_scc_break *) input       WRE,
+	(* abc_scc_break *)
+	input  [3:0] DI,
+	(* abc_scc_break *)
+	input  [3:0] WAD,
+	(* abc_scc_break *)
+	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
 	output [3:0] DO
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index ab04808f4..c7f3bdad2 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,11 +143,13 @@ endmodule
 
 (* abc_box_id = 1, lib_whitebox *)
 module \$__ICE40_FULL_ADDER (
-	(* abc_carry *) output CO,
+	(* abc_carry *)
+	output CO,
 	output O,
 	input A,
 	input B,
-	(* abc_carry *) input CI
+	(* abc_carry *)
+	input CI
 );
 	SB_CARRY carry (
 		.I0(A),
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index bec9ea1a0..e3897d9a6 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -183,9 +183,11 @@ endmodule
 
 (* abc_box_id = 4, lib_whitebox *)
 module CARRY4(
-  (* abc_carry *) output [3:0] CO,
+  (* abc_carry *)
+  output [3:0] CO,
   output [3:0] O,
-  (* abc_carry *) input CI,
+  (* abc_carry *)
+  input        CI,
   input        CYINIT,
   input  [3:0] DI, S
 );
@@ -298,9 +300,11 @@ endmodule
 (* abc_box_id = 5 *)
 module RAM32X1D (
   output DPO, SPO,
-  (* abc_scc_break *) input D,
+  (* abc_scc_break *)
+  input  D,
   input  WCLK,
-  (* abc_scc_break *) input WE,
+  (* abc_scc_break *)
+  input  WE,
   input  A0, A1, A2, A3, A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
@@ -318,7 +322,8 @@ endmodule
 (* abc_box_id = 6 *)
 module RAM64X1D (
   output DPO, SPO,
-  (* abc_scc_break *) input D,
+  (* abc_scc_break *)
+  input  D,
   input  WCLK,
   (* abc_scc_break *) input WE,
   input  A0, A1, A2, A3, A4, A5,
@@ -338,9 +343,11 @@ endmodule
 (* abc_box_id = 7 *)
 module RAM128X1D (
   output       DPO, SPO,
-  (* abc_scc_break *) input D,
+  (* abc_scc_break *)
+  input        D,
   input        WCLK,
-  (* abc_scc_break *) input WE,
+  (* abc_scc_break *)
+  input        WE,
   input  [6:0] A, DPRA
 );
   parameter INIT = 128'h0;

From 509c353fe981c95ca667a637bf2b47477962a60b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 11:23:50 -0700
Subject: [PATCH 076/111] Forgot one

---
 techlibs/xilinx/cells_sim.v | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index e3897d9a6..3ad96d7fb 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -325,7 +325,8 @@ module RAM64X1D (
   (* abc_scc_break *)
   input  D,
   input  WCLK,
-  (* abc_scc_break *) input WE,
+  (* abc_scc_break *)
+  input  WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );

From 43927e5910f54b41530dd4dbba8059b2c80d8c26 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 11:26:32 -0700
Subject: [PATCH 077/111] Bump gcc from 4.8 to 4.9 as undefined reference

... to `__warn_memset_zero_len'.
Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
---
 .travis.yml | 42 +++++++-----------------------------------
 1 file changed, 7 insertions(+), 35 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 957735f1d..a4e9ffe40 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -18,7 +18,7 @@ matrix:
       addons:
         apt:
           packages:
-            - g++-4.8
+            - g++-4.9
             - gperf
             - build-essential
             - bison
@@ -37,35 +37,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8"
-
-    # Latest gcc-6 on Travis Linux
-    - os: linux
-      addons:
-        apt:
-          sources:
-            - ubuntu-toolchain-r-test
-          packages:
-            - g++-6
-            - gperf
-            - build-essential
-            - bison
-            - flex
-            - libreadline-dev
-            - gawk
-            - tcl-dev
-            - libffi-dev
-            - git
-            - graphviz
-            - xdot
-            - pkg-config
-            - python
-            - python3
-            - libboost-system-dev
-            - libboost-python-dev
-            - libboost-filesystem-dev
-      env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-6 && CXX=g++-6"
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9"
 
     # Latest gcc supported on Travis Linux
     - os: linux
@@ -74,7 +46,7 @@ matrix:
           sources:
             - ubuntu-toolchain-r-test
           packages:
-            - g++-7
+            - g++-9
             - gperf
             - build-essential
             - bison
@@ -93,7 +65,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-7 && CXX=g++-7"
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-9 && CXX=g++-9"
 
     # Clang which ships on Trusty Linux
     - os: linux
@@ -129,9 +101,9 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-trusty-5.0
+            - llvm-toolchain-bionic-8.0
           packages:
-            - clang-5.0
+            - clang-8.0
             - gperf
             - build-essential
             - bison
@@ -150,7 +122,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=clang && CC=clang-5.0 && CXX=clang++-5.0"
+        - MATRIX_EVAL="CONFIG=clang && CC=clang-8.0 && CXX=clang++-8.0"
 
 #   # Latest clang on Mac OS X
 #   - os: osx

From bf40f2f895ab5a5ebe047e9281d5ba8707e04e94 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 11:52:08 -0700
Subject: [PATCH 078/111] bionic -> xenial as its on whitelist

---
 .travis.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.travis.yml b/.travis.yml
index a4e9ffe40..bc07c741e 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -101,7 +101,7 @@ matrix:
       addons:
         apt:
           sources:
-            - llvm-toolchain-bionic-8.0
+            - llvm-toolchain-xenial-8
           packages:
             - clang-8.0
             - gperf

From fdc438e551f5ee13a62e216b861237b2195d9131 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 12:16:02 -0700
Subject: [PATCH 079/111] Bump to gcc-5 as `__warn_memset_zero_len' symbol not
 in 16.04!?!

---
 .travis.yml | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index bc07c741e..093dd2dbf 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -13,12 +13,14 @@ env:
 
 matrix:
   include:
-    # Latest gcc-4.8, earliest version supported by Travis
+    # Earliest gcc version that works
+    #   4.8 and 4.9 fails to compile iverilog giving:
+    #   "undefined reference to `__warn_memset_zero_len'"
     - os: linux
       addons:
         apt:
           packages:
-            - g++-4.9
+            - g++-5
             - gperf
             - build-essential
             - bison
@@ -37,7 +39,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9"
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-5 && CXX=g++-5"
 
     # Latest gcc supported on Travis Linux
     - os: linux

From fcb102d60e7a6295fd78214917df2a15834808d0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 12:23:15 -0700
Subject: [PATCH 080/111] Remove .0 from clang-8.0

---
 .travis.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 093dd2dbf..c5fe244fb 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -105,7 +105,7 @@ matrix:
           sources:
             - llvm-toolchain-xenial-8
           packages:
-            - clang-8.0
+            - clang-8
             - gperf
             - build-essential
             - bison
@@ -124,7 +124,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=clang && CC=clang-8.0 && CXX=clang++-8.0"
+        - MATRIX_EVAL="CONFIG=clang && CC=clang-8 && CXX=clang++-8"
 
 #   # Latest clang on Mac OS X
 #   - os: osx

From b3dc28cf65dcadd9038ff068be239e2f81f504f4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 12:26:45 -0700
Subject: [PATCH 081/111] Revert "Bump to gcc-5 as `__warn_memset_zero_len'
 symbol not in 16.04!?!"

This reverts commit c82b2fa31f8965be2680c87af6cd9ac5d26ead4d.
---
 .travis.yml | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index c5fe244fb..61ade0e7a 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -13,14 +13,12 @@ env:
 
 matrix:
   include:
-    # Earliest gcc version that works
-    #   4.8 and 4.9 fails to compile iverilog giving:
-    #   "undefined reference to `__warn_memset_zero_len'"
+    # Latest gcc-4.8, earliest version supported by Travis
     - os: linux
       addons:
         apt:
           packages:
-            - g++-5
+            - g++-4.9
             - gperf
             - build-essential
             - bison
@@ -39,7 +37,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-5 && CXX=g++-5"
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9"
 
     # Latest gcc supported on Travis Linux
     - os: linux

From 4a4e28b55eb24ec4e83b092bf8478bb8149669c0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 12:28:17 -0700
Subject: [PATCH 082/111] Revert earliest to gcc-4.8, compile iverilog with
 default compiler

---
 .travis.yml      | 4 ++--
 .travis/setup.sh | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 61ade0e7a..c253b2ff7 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -18,7 +18,7 @@ matrix:
       addons:
         apt:
           packages:
-            - g++-4.9
+            - g++-4.8
             - gperf
             - build-essential
             - bison
@@ -37,7 +37,7 @@ matrix:
             - libboost-python-dev
             - libboost-filesystem-dev
       env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9"
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8"
 
     # Latest gcc supported on Travis Linux
     - os: linux
diff --git a/.travis/setup.sh b/.travis/setup.sh
index 4af0b8ee9..02879b974 100755
--- a/.travis/setup.sh
+++ b/.travis/setup.sh
@@ -51,7 +51,7 @@ fi
 		git clone git://github.com/steveicarus/iverilog.git
 		cd iverilog
 		autoconf
-		./configure --prefix=$HOME/.local-bin
+		CC=gcc CXX=g++ ./configure --prefix=$HOME/.local-bin
 		make
 		make install
 		echo

From 967a36c12572bb7e1bd69921ae75dda767b4243f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:15:41 -0700
Subject: [PATCH 083/111] indo -> into

---
 passes/pmgen/README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md
index 27ed77091..0856c9ba3 100644
--- a/passes/pmgen/README.md
+++ b/passes/pmgen/README.md
@@ -195,7 +195,7 @@ create matches for different sections of a cell. For example:
 
 The first argument to `slice` is the local variable name used to identify the
 slice. The second argument is the number of slices that should be created for
-this cell. The `set` statement can be used to copy that index indo a state
+this cell. The `set` statement can be used to copy that index into a state
 variable so that later matches and/or code blocks can refer to it.
 
 A similar mechanism is "choices", where a list of options is given as

From d7051b90de19ba0faed0a4eff4af7c3bc92dd3fd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 16:41:32 -0700
Subject: [PATCH 084/111] Add undocumented feature

---
 techlibs/xilinx/synth_xilinx.cc | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7ba67409b..87f4af8f7 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -105,6 +105,7 @@ struct SynthXilinxPass : public ScriptPass
 
 	std::string top_opt, edif_file, blif_file, family;
 	bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
+	bool flatten_before_abc;
 	int widemux;
 
 	void clear_flags() YS_OVERRIDE
@@ -123,6 +124,7 @@ struct SynthXilinxPass : public ScriptPass
 		nocarry = false;
 		nowidelut = false;
 		abc9 = false;
+		flatten_before_abc = false;
 		widemux = 0;
 	}
 
@@ -162,6 +164,10 @@ struct SynthXilinxPass : public ScriptPass
 				flatten = true;
 				continue;
 			}
+			if (args[argidx] == "-flatten_before_abc") {
+				flatten_before_abc = true;
+				continue;
+			}
 			if (args[argidx] == "-retime") {
 				retime = true;
 				continue;
@@ -385,6 +391,8 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_luts")) {
 			run("opt_expr -mux_undef");
+			if (flatten_before_abc)
+				run("flatten");
 			if (help_mode)
 				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
 			else if (abc9) {

From dc87372a97d515563ccccd517ef8f35662870fe6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 24 Aug 2019 15:05:44 -0700
Subject: [PATCH 085/111] Wire with init on FF part, 1'bx on non-FF part

---
 tests/sat/initval.v | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tests/sat/initval.v b/tests/sat/initval.v
index fcec9dd8c..81f71b5ba 100644
--- a/tests/sat/initval.v
+++ b/tests/sat/initval.v
@@ -1,4 +1,4 @@
-module test(input clk, input [3:0] bar, output [3:0] foo);
+module test(input clk, input [3:0] bar, output [3:0] foo, asdf);
   reg [3:0] foo = 0;
   reg [3:0] last_bar = 0;
   reg [3:0] asdf = 4'b1xxx;
@@ -12,6 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
   always @(posedge clk)
     last_bar <= bar;
 
+  always @(posedge clk)
+    asdf[3] <= bar[3];
   always @*
     asdf[2:0] = 3'b111;
 

From 1979e0b1f2482dbf0562f5116ab444280a377773 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 26 Aug 2019 10:37:53 +0200
Subject: [PATCH 086/111] Yosys 0.9

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 21f1c5f46..a67315415 100644
--- a/Makefile
+++ b/Makefile
@@ -114,7 +114,7 @@ LDFLAGS += -rdynamic
 LDLIBS += -lrt
 endif
 
-YOSYS_VER := 0.8+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 4d4665b.. 2> /dev/null | wc -l; })
+YOSYS_VER := 0.9
 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o
 

From bd3773a17f220f1fa9b478b3785acac42ca3bd7f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 26 Aug 2019 10:44:23 -0700
Subject: [PATCH 087/111] Remove dupe in CHANGELOG, missing end quote

---
 CHANGELOG | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index c4882acab..113aae820 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -12,11 +12,10 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)
     - Added "synth -abc9" (experimental)
-    - Added "script -scriptwire
+    - Added "script -scriptwire"
     - Added "synth_xilinx -nocarry"
     - Added "synth_xilinx -nowidelut"
     - Added "synth_ecp5 -nowidelut"
-    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
     - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
     - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
     - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)

From 528f1c86877d247700bd9445e03c85b3eb437b5c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 26 Aug 2019 13:45:16 -0700
Subject: [PATCH 088/111] Improve tests to check that clkbuf is connected to
 expected

---
 tests/techmap/clkbufmap.ys | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys
index 46ff4d694..5847c3ce5 100644
--- a/tests/techmap/clkbufmap.ys
+++ b/tests/techmap/clkbufmap.ys
@@ -18,9 +18,15 @@ design -save ref
 
 design -load ref
 clkbufmap -buf clkbuf o:i
-select -assert-count 1 w:clk1 %a %co t:clkbuf %i
-select -assert-count 1 w:clk2 %a %co t:clkbuf %i
 select -assert-count 2 t:clkbuf
+select -set clk1 w:clk1 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
+select -assert-count 1 @clk1                        # Check there is one such fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i    # And that one fanout is 's0'
+select -set clk2 w:clk2 %a %co t:clkbuf %i
+select -assert-count 1 @clk2
+select -assert-count 1 @clk2 %x:+[o] %co c:s* %i
+select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i
 
 # ----------------------
 
@@ -28,9 +34,12 @@ design -load ref
 setattr -set clkbuf_inhibit 0 w:clk1
 setattr -set clkbuf_inhibit 1 w:clk2
 clkbufmap -buf clkbuf o:i
-select -assert-count 1 w:clk1 %a %co t:clkbuf %i
-select -assert-count 0 w:clk2 %a %co t:clkbuf %i
 select -assert-count 1 t:clkbuf
+select -set clk1 w:clk1 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
+select -assert-count 1 @clk1                        # Check there is one such fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i    # And that one fanout is 's0'
+select -assert-count 0 w:clk2 %a %co t:clkbuf %i
 
 # ----------------------
 
@@ -38,9 +47,15 @@ design -load ref
 setattr -set clkbuf_inhibit 1 w:clk1
 setattr -set buffer_type "bufg" w:clk2
 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
-select -assert-count 1 w:clk1 %a %co t:clkbuf %i
-select -assert-count 1 w:clk2 %a %co t:clkbuf %i
 select -assert-count 2 t:clkbuf
+select -set clk1 w:clk1 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
+select -assert-count 1 @clk1                        # Check there is one such fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i    # And that one fanout is 's0'
+select -set clk2 w:clk2 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
+select -assert-count 1 @clk2                        # Check there is one such fanout
+select -assert-count 1 @clk2 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
+select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i    # And that one fanout is 's0'
 
 # ----------------------
 

From fdbcf789099d327bd5e9f2e0658cdad754b09db2 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 27 Aug 2019 10:13:23 +0200
Subject: [PATCH 089/111] Add "make bumpversion"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 CodingReadme | 1 +
 Makefile     | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/CodingReadme b/CodingReadme
index b64e79178..8212436e5 100644
--- a/CodingReadme
+++ b/CodingReadme
@@ -390,6 +390,7 @@ Finally run all tests with "make config-{clang,gcc,gcc-4.8}":
 Release:
 
 	- set YOSYS_VER to x.y.z in Makefile
+	- remove "bumpversion" target from Makefile
 	- update version string in CHANGELOG
 	git commit -am "Yosys x.y.z"
 
diff --git a/Makefile b/Makefile
index 48a4f3a1c..e56db424d 100644
--- a/Makefile
+++ b/Makefile
@@ -119,6 +119,9 @@ YOSYS_VER := 0.9+1
 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o
 
+bumpversion:
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 8a4c6e6.. | wc -l`/;" Makefile
+
 # set 'ABCREV = default' to use abc/ as it is
 #
 # Note: If you do ABC development, make sure that 'abc' in this directory

From fc001b473187f13fa0e6f01063ffc9640fb11ef8 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 27 Aug 2019 13:07:06 +0100
Subject: [PATCH 090/111] ecp5: Add GSR support

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/Makefile.inc  |   3 +-
 techlibs/ecp5/brams_map.v   |  10 +--
 techlibs/ecp5/cells_bb.v    |  20 ++++++
 techlibs/ecp5/cells_map.v   |  76 ++++++++++----------
 techlibs/ecp5/ecp5_gsr.cc   | 135 ++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/synth_ecp5.cc |   2 +
 6 files changed, 202 insertions(+), 44 deletions(-)
 create mode 100644 techlibs/ecp5/ecp5_gsr.cc

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 73e18112f..c41d16076 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -1,5 +1,6 @@
 
-OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o
+OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o \
+        techlibs/ecp5/ecp5_gsr.o
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index b2c136863..0353cbadb 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -33,7 +33,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
 			.WRITEMODE_B("READBEFOREWRITE"),
-			.GSR("DISABLED")
+			.GSR("AUTO")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_1.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
@@ -50,7 +50,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
 			.WRITEMODE_B("READBEFOREWRITE"),
-			.GSR("DISABLED")
+			.GSR("AUTO")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_2.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
@@ -67,7 +67,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
 			.WRITEMODE_B("READBEFOREWRITE"),
-			.GSR("DISABLED")
+			.GSR("AUTO")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_4.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
@@ -84,7 +84,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
 			.WRITEMODE_B("READBEFOREWRITE"),
-			.GSR("DISABLED")
+			.GSR("AUTO")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_9.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
@@ -101,7 +101,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
 			.WRITEMODE_B("READBEFOREWRITE"),
-			.GSR("DISABLED")
+			.GSR("AUTO")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_18.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 223e19b9e..8557053b6 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -664,3 +664,23 @@ module PCSCLKDIV (
 );
 	parameter GSR = "DISABLED";
 endmodule
+
+// Note: this module is not marked keep as we want it swept away in synth (sim use only)
+(* blackbox *)
+module PUR (
+	input PUR
+);
+	parameter RST_PULSE = 1;
+endmodule
+
+(* blackbox, keep *)
+module GSR (
+	input GSR
+);
+endmodule
+
+(* blackbox, keep *)
+module SGSR (
+	input GSR, CLK
+);
+endmodule
\ No newline at end of file
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 6985fbbc8..0a92d906d 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -1,51 +1,51 @@
-module  \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
 
-module  \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module  \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
 
-module  \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module  \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
 
-module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
-module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
 // TODO: Diamond flip-flops
 // module FD1P3AX(); endmodule
diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc
new file mode 100644
index 000000000..8b8927d31
--- /dev/null
+++ b/techlibs/ecp5/ecp5_gsr.cc
@@ -0,0 +1,135 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2019  David Shah <david@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct Ecp5GsrPass : public Pass {
+	Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ecp5_gsr [options] [selection]\n");
+		log("\n");
+		log("Trim active low async resets connected to GSR and resolve GSR parameter,\n");
+		log("if a GSR or SGSR primitive is used in the design.\n");
+		log("\n");
+		log("If any cell has the GSR parameter set to \"AUTO\", this will be resolved\n");
+		log("to \"ENABLED\" if a GSR primitive is present and the (* nogsr *) attribute\n");
+		log("is not set, otherwise it will be resolved to \"DISABLED\".\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-singleton") {
+			// 	singleton_mode = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			log("Handling GSR in %s.\n", log_id(module));
+
+			SigMap sigmap(module);
+
+			SigBit gsr;
+			bool found_gsr = false;
+
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type != ID(GSR) && cell->type != ID(SGSR))
+					continue;
+				if (found_gsr)
+					log_error("Found more than one GSR or SGSR cell in module %s.\n", log_id(module));
+				found_gsr = true;
+				SigSpec sig_gsr = cell->getPort(ID(GSR));
+				if (GetSize(sig_gsr) < 1)
+					log_error("GSR cell %s has disconnected GSR input.\n", log_id(cell));
+				gsr = sigmap(sig_gsr[0]);
+			}
+
+			// Resolve GSR parameter
+
+			for (auto cell : module->selected_cells())
+			{
+				if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO")
+					continue;
+				
+				bool gsren = found_gsr;
+				if (cell->get_bool_attribute("\\nogsr"))
+					gsren = false;
+				cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED"));
+				
+			}
+
+			if (!found_gsr)
+				continue;
+
+			// For finding active low FF inputs
+			pool<SigBit> inverted_gsr;
+
+			log_debug("GSR net in module %s is %s.\n", log_id(module), log_signal(gsr));
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type != ID($_NOT_))
+					continue;
+				SigSpec sig_a = cell->getPort(ID(A)), sig_y = cell->getPort(ID(Y));
+				if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1)
+					continue;
+				SigBit a = sigmap(sig_a[0]);
+				if (a == gsr)
+					inverted_gsr.insert(sigmap(sig_y[0]));
+			}
+
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type != ID(TRELLIS_FF))
+					continue;
+				if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "ENABLED")
+					continue;
+				if (!cell->hasParam(ID(SRMODE)) || cell->getParam(ID(SRMODE)).decode_string() != "ASYNC")
+					continue;
+				SigSpec sig_lsr = cell->getPort(ID(LSR));
+				if (GetSize(sig_lsr) < 1)
+					continue;
+				SigBit lsr = sigmap(sig_lsr[0]);
+				if (!inverted_gsr.count(lsr))
+					continue;
+				cell->setParam(ID(SRMODE), Const("SYNC"));
+				cell->unsetPort(ID(LSR));
+			}
+
+		}
+	}
+} Ecp5GsrPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 143d1f95c..a8075e86e 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -271,6 +271,8 @@ struct SynthEcp5Pass : public ScriptPass
 			run("opt_expr -undriven -mux_undef");
 			run("simplemap");
 			run("ecp5_ffinit");
+			run("ecp5_gsr");
+			run("opt_clean");
 		}
 
 		if (check_label("map_luts"))

From 5fb4b12cb50b870b546d76f9c702678d8f0aa60a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <marcin@symbioticeda.com>
Date: Tue, 27 Aug 2019 17:26:47 +0200
Subject: [PATCH 091/111] improve clkbuf_inhibit propagation upwards through
 hierarchy

---
 passes/techmap/clkbufmap.cc | 13 ++++++++++++-
 tests/techmap/clkbufmap.ys  | 38 ++++++++++++++++++++++++++++++++-----
 2 files changed, 45 insertions(+), 6 deletions(-)

diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc
index 82b3dcdf7..246932d81 100644
--- a/passes/techmap/clkbufmap.cc
+++ b/passes/techmap/clkbufmap.cc
@@ -166,13 +166,24 @@ struct ClkbufmapPass : public Pass {
 
 			// Insert buffers.
 			std::vector<pair<Wire *, Wire *>> input_queue;
-			for (auto wire : module->selected_wires())
+			// Copy current wire list, as we will be adding new ones during iteration.
+			std::vector<Wire *> wires(module->wires());
+			for (auto wire : wires)
 			{
 				// Should not happen.
 				if (wire->port_input && wire->port_output)
 					continue;
+				bool process_wire = module->selected(wire);
 				if (!select && wire->get_bool_attribute("\\clkbuf_inhibit"))
+					process_wire = false;
+				if (!process_wire) {
+					// This wire is supposed to be bypassed, so make sure we don't buffer it in
+					// some buffer higher up in the hierarchy.
+					if (wire->port_output)
+						for (int i = 0; i < GetSize(wire); i++)
+							buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
 					continue;
+				}
 
 				pool<int> input_bits;
 
diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys
index 5847c3ce5..f1277864e 100644
--- a/tests/techmap/clkbufmap.ys
+++ b/tests/techmap/clkbufmap.ys
@@ -3,11 +3,26 @@ module clkbuf (input i, (* clkbuf_driver *) output o); endmodule
 module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule
 module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule
 module latch (input e, d, output q); endmodule
+module clkgen (output o); endmodule
 
-module top(input clk1, clk2, clk3, d, e, output [2:0] q);
+module top(input clk1, clk2, clk3, d, e, output [4:0] q);
+wire clk4, clk5, clk6;
 dff s0 (.clk(clk1), .d(d), .q(q[0]));
 dffe s1 (.c(clk2), .d(d), .e(e), .q(q[1]));
 latch s2 (.e(clk3), .d(d), .q(q[2]));
+sub s3 (.sclk4(clk4), .sclk5(clk5), .sclk6(clk6), .sd(d), .sq(q[3]));
+dff s4 (.clk(clk4), .d(d), .q(q[4]));
+dff s5 (.clk(clk5), .d(d), .q(q[4]));
+dff s6 (.clk(clk6), .d(d), .q(q[4]));
+endmodule
+
+module sub(output sclk4, output sclk5, output sclk6, input sd, output sq);
+wire tmp;
+clkgen s7(.o(sclk4));
+clkgen s8(.o(sclk5));
+clkgen s9(.o(tmp));
+clkbuf s10(.i(tmp), .o(sclk6));
+dff s11(.clk(sclk4), .d(sd), .q(sq));
 endmodule
 EOT
 
@@ -18,7 +33,8 @@ design -save ref
 
 design -load ref
 clkbufmap -buf clkbuf o:i
-select -assert-count 2 t:clkbuf
+select -assert-count 3 top/t:clkbuf
+select -assert-count 2 sub/t:clkbuf
 select -set clk1 w:clk1 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
 select -assert-count 1 @clk1                        # Check there is one such fanout
 select -assert-count 1 @clk1 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
@@ -27,6 +43,14 @@ select -set clk2 w:clk2 %a %co t:clkbuf %i
 select -assert-count 1 @clk2
 select -assert-count 1 @clk2 %x:+[o] %co c:s* %i
 select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i
+select -set clk5 w:clk5 %a %ci t:clkbuf %i
+select -assert-count 1 @clk5
+select -assert-count 1 @clk5 %x:+[o] %co c:s5 %i
+select -assert-count 1 @clk5 %x:+[i] %ci c:s3 %i
+select -set sclk4 w:sclk4 %a %ci t:clkbuf %i
+select -assert-count 1 @sclk4
+select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i
+select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i
 
 # ----------------------
 
@@ -34,7 +58,7 @@ design -load ref
 setattr -set clkbuf_inhibit 0 w:clk1
 setattr -set clkbuf_inhibit 1 w:clk2
 clkbufmap -buf clkbuf o:i
-select -assert-count 1 t:clkbuf
+select -assert-count 2 top/t:clkbuf
 select -set clk1 w:clk1 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
 select -assert-count 1 @clk1                        # Check there is one such fanout
 select -assert-count 1 @clk1 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
@@ -47,7 +71,8 @@ design -load ref
 setattr -set clkbuf_inhibit 1 w:clk1
 setattr -set buffer_type "bufg" w:clk2
 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
-select -assert-count 2 t:clkbuf
+select -assert-count 3 top/t:clkbuf
+select -assert-count 2 sub/t:clkbuf
 select -set clk1 w:clk1 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
 select -assert-count 1 @clk1                        # Check there is one such fanout
 select -assert-count 1 @clk1 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
@@ -62,7 +87,10 @@ select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i    # And that one fanout is 's0
 design -load ref
 setattr -set buffer_type "none" w:clk1
 setattr -set buffer_type "bufr" w:clk2
+setattr -set buffer_type "bufr" w:sclk4
+setattr -set buffer_type "bufr" w:sclk5
 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
 select -assert-count 0 w:clk1 %a %co t:clkbuf %i
 select -assert-count 0 w:clk2 %a %co t:clkbuf %i
-select -assert-count 0 t:clkbuf
+select -assert-count 0 top/t:clkbuf
+select -assert-count 1 sub/t:clkbuf

From 00387f39277ab817b3b17e72b59793e6d5dfcde8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 27 Aug 2019 09:24:32 -0700
Subject: [PATCH 092/111] Revert to using clean

---
 tests/sat/initval.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 3d88aa971..2079d2f34 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -1,4 +1,4 @@
 read_verilog -sv initval.v
-proc;
+proc;;
 
 sat -seq 10 -prove-asserts

From 28133432bea4a3fa01cd2f5e82a52a853cfccb84 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 27 Aug 2019 09:24:59 -0700
Subject: [PATCH 093/111] Ignore all 1'bx in (* init *)

---
 passes/sat/sat.cc | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index bcc690fa3..430bba1e8 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -268,9 +268,7 @@ struct SatHelper
 				RTLIL::SigSpec removed_bits;
 				for (int i = 0; i < lhs.size(); i++) {
 					RTLIL::SigSpec bit = lhs.extract(i, 1);
-					if (bit.is_fully_const() && rhs[i] == State::Sx)
-						rhs[i] = bit;
-					if (!satgen.initial_state.check_all(bit)) {
+					if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) {
 						removed_bits.append(bit);
 						lhs.remove(i, 1);
 						rhs.remove(i, 1);

From d361f5ab795f5b823a594f1fee75f93a78995481 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <marcin@symbioticeda.com>
Date: Tue, 27 Aug 2019 18:08:51 +0200
Subject: [PATCH 094/111] xilinx: Add SRLC16E primitive.

Fixes #1331.
---
 techlibs/xilinx/cells_sim.v | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index aeef7f885..973e17212 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -394,7 +394,27 @@ module SRL16E (
       always @(negedge CLK) if (CE) r <= { r[14:0], D };
     end
     else
-        always @(posedge CLK) if (CE) r <= { r[14:0], D };
+      always @(posedge CLK) if (CE) r <= { r[14:0], D };
+  endgenerate
+endmodule
+
+module SRLC16E (
+  output Q,
+  output Q15,
+  input A0, A1, A2, A3, CE, CLK, D
+);
+  parameter [15:0] INIT = 16'h0000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+
+  reg [15:0] r = INIT;
+  assign Q15 = r[15];
+  assign Q = r[{A3,A2,A1,A0}];
+  generate
+    if (IS_CLK_INVERTED) begin
+      always @(negedge CLK) if (CE) r <= { r[14:0], D };
+    end
+    else
+      always @(posedge CLK) if (CE) r <= { r[14:0], D };
   endgenerate
 endmodule
 

From c499dc3e73390c3bc9bf8045f2e4cad963c1fbad Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 28 Aug 2019 09:45:22 +0200
Subject: [PATCH 095/111] Add $dlatch support to async2sync

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/async2sync.cc | 37 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
index d045d0dcb..24ae6e448 100644
--- a/passes/sat/async2sync.cc
+++ b/passes/sat/async2sync.cc
@@ -39,7 +39,7 @@ struct Async2syncPass : public Pass {
 		log("reset value in the next cycle regardless of the data-in value at the time of\n");
 		log("the clock edge.\n");
 		log("\n");
-		log("Currently only $adff and $dffsr cells are supported by this pass.\n");
+		log("Currently only $adff, $dffsr, and $dlatch cells are supported by this pass.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -169,6 +169,41 @@ struct Async2syncPass : public Pass {
 					cell->type = "$dff";
 					continue;
 				}
+
+				if (cell->type.in("$dlatch"))
+				{
+					bool en_pol = cell->parameters["\\EN_POLARITY"].as_bool();
+
+					SigSpec sig_en = cell->getPort("\\EN");
+					SigSpec sig_d = cell->getPort("\\D");
+					SigSpec sig_q = cell->getPort("\\Q");
+
+					log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
+							log_id(module), log_id(cell), log_id(cell->type),
+							log_signal(sig_en), log_signal(sig_d), log_signal(sig_q));
+
+					Const init_val;
+					for (int i = 0; i < GetSize(sig_q); i++) {
+						SigBit bit = sigmap(sig_q[i]);
+						init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
+						del_initbits.insert(bit);
+					}
+
+					Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
+					new_q->attributes["\\init"] = init_val;
+
+					if (en_pol) {
+						module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q);
+					} else {
+						module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q);
+					}
+
+					cell->setPort("\\Q", new_q);
+					cell->unsetPort("\\EN");
+					cell->unsetParam("\\EN_POLARITY");
+					cell->type = "$ff";
+					continue;
+				}
 			}
 
 			for (auto wire : module->wires())

From 0fda0e821cee249dd722c8b52e941c35bd9d8df0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 28 Aug 2019 10:03:27 +0200
Subject: [PATCH 096/111] Add "paramap" pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/techmap/attrmap.cc | 185 ++++++++++++++++++++++++--------------
 1 file changed, 118 insertions(+), 67 deletions(-)

diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
index a38638e0b..3a2835733 100644
--- a/passes/techmap/attrmap.cc
+++ b/passes/techmap/attrmap.cc
@@ -143,6 +143,82 @@ void attrmap_apply(string objname, vector<std::unique_ptr<AttrmapAction>> &actio
 	attributes.swap(new_attributes);
 }
 
+void log_attrmap_paramap_options()
+{
+	log("    -tocase <name>\n");
+	log("        Match attribute names case-insensitively and set it to the specified\n");
+	log("        name.\n");
+	log("\n");
+	log("    -rename <old_name> <new_name>\n");
+	log("        Rename attributes as specified\n");
+	log("\n");
+	log("    -map <old_name>=<old_value> <new_name>=<new_value>\n");
+	log("        Map key/value pairs as indicated.\n");
+	log("\n");
+	log("    -imap <old_name>=<old_value> <new_name>=<new_value>\n");
+	log("        Like -map, but use case-insensitive match for <old_value> when\n");
+	log("        it is a string value.\n");
+	log("\n");
+	log("    -remove <name>=<value>\n");
+	log("        Remove attributes matching this pattern.\n");
+}
+
+bool parse_attrmap_paramap_options(size_t &argidx, std::vector<std::string> &args, vector<std::unique_ptr<AttrmapAction>> &actions)
+{
+	std::string arg = args[argidx];
+	if (arg == "-tocase" && argidx+1 < args.size()) {
+		auto action = new AttrmapTocase;
+		action->name = args[++argidx];
+		actions.push_back(std::unique_ptr<AttrmapAction>(action));
+		return true;
+	}
+	if (arg == "-rename" && argidx+2 < args.size()) {
+		auto action = new AttrmapRename;
+		action->old_name = args[++argidx];
+		action->new_name = args[++argidx];
+		actions.push_back(std::unique_ptr<AttrmapAction>(action));
+		return true;
+	}
+	if ((arg == "-map" || arg == "-imap") && argidx+2 < args.size()) {
+		string arg1 = args[++argidx];
+		string arg2 = args[++argidx];
+		string val1, val2;
+		size_t p = arg1.find("=");
+		if (p != string::npos) {
+			val1 = arg1.substr(p+1);
+			arg1 = arg1.substr(0, p);
+		}
+		p = arg2.find("=");
+		if (p != string::npos) {
+			val2 = arg2.substr(p+1);
+			arg2 = arg2.substr(0, p);
+		}
+		auto action = new AttrmapMap;
+		action->imap = (arg == "-map");
+		action->old_name = arg1;
+		action->new_name = arg2;
+		action->old_value = val1;
+		action->new_value = val2;
+		actions.push_back(std::unique_ptr<AttrmapAction>(action));
+		return true;
+	}
+	if (arg == "-remove" && argidx+1 < args.size()) {
+		string arg1 = args[++argidx], val1;
+		size_t p = arg1.find("=");
+		if (p != string::npos) {
+			val1 = arg1.substr(p+1);
+			arg1 = arg1.substr(0, p);
+		}
+		auto action = new AttrmapRemove;
+		action->name = arg1;
+		action->has_value = (p != string::npos);
+		action->value = val1;
+		actions.push_back(std::unique_ptr<AttrmapAction>(action));
+		return true;
+	}
+	return false;
+}
+
 struct AttrmapPass : public Pass {
 	AttrmapPass() : Pass("attrmap", "renaming attributes") { }
 	void help() YS_OVERRIDE
@@ -154,22 +230,7 @@ struct AttrmapPass : public Pass {
 		log("This command renames attributes and/or mapps key/value pairs to\n");
 		log("other key/value pairs.\n");
 		log("\n");
-		log("    -tocase <name>\n");
-		log("        Match attribute names case-insensitively and set it to the specified\n");
-		log("        name.\n");
-		log("\n");
-		log("    -rename <old_name> <new_name>\n");
-		log("        Rename attributes as specified\n");
-		log("\n");
-		log("    -map <old_name>=<old_value> <new_name>=<new_value>\n");
-		log("        Map key/value pairs as indicated.\n");
-		log("\n");
-		log("    -imap <old_name>=<old_value> <new_name>=<new_value>\n");
-		log("        Like -map, but use case-insensitive match for <old_value> when\n");
-		log("        it is a string value.\n");
-		log("\n");
-		log("    -remove <name>=<value>\n");
-		log("        Remove attributes matching this pattern.\n");
+		log_attrmap_paramap_options();
 		log("\n");
 		log("    -modattr\n");
 		log("        Operate on module attributes instead of attributes on wires and cells.\n");
@@ -190,58 +251,9 @@ struct AttrmapPass : public Pass {
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			std::string arg = args[argidx];
-			if (arg == "-tocase" && argidx+1 < args.size()) {
-				auto action = new AttrmapTocase;
-				action->name = args[++argidx];
-				actions.push_back(std::unique_ptr<AttrmapAction>(action));
+			if (parse_attrmap_paramap_options(argidx, args, actions))
 				continue;
-			}
-			if (arg == "-rename" && argidx+2 < args.size()) {
-				auto action = new AttrmapRename;
-				action->old_name = args[++argidx];
-				action->new_name = args[++argidx];
-				actions.push_back(std::unique_ptr<AttrmapAction>(action));
-				continue;
-			}
-			if ((arg == "-map" || arg == "-imap") && argidx+2 < args.size()) {
-				string arg1 = args[++argidx];
-				string arg2 = args[++argidx];
-				string val1, val2;
-				size_t p = arg1.find("=");
-				if (p != string::npos) {
-					val1 = arg1.substr(p+1);
-					arg1 = arg1.substr(0, p);
-				}
-				p = arg2.find("=");
-				if (p != string::npos) {
-					val2 = arg2.substr(p+1);
-					arg2 = arg2.substr(0, p);
-				}
-				auto action = new AttrmapMap;
-				action->imap = (arg == "-map");
-				action->old_name = arg1;
-				action->new_name = arg2;
-				action->old_value = val1;
-				action->new_value = val2;
-				actions.push_back(std::unique_ptr<AttrmapAction>(action));
-				continue;
-			}
-			if (arg == "-remove" && argidx+1 < args.size()) {
-				string arg1 = args[++argidx], val1;
-				size_t p = arg1.find("=");
-				if (p != string::npos) {
-					val1 = arg1.substr(p+1);
-					arg1 = arg1.substr(0, p);
-				}
-				auto action = new AttrmapRemove;
-				action->name = arg1;
-				action->has_value = (p != string::npos);
-				action->value = val1;
-				actions.push_back(std::unique_ptr<AttrmapAction>(action));
-				continue;
-			}
-			if (arg == "-modattr") {
+			if (args[argidx] == "-modattr") {
 				modattr_mode = true;
 				continue;
 			}
@@ -287,4 +299,43 @@ struct AttrmapPass : public Pass {
 	}
 } AttrmapPass;
 
+struct ParamapPass : public Pass {
+	ParamapPass() : Pass("paramap", "renaming cell parameters") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    paramap [options] [selection]\n");
+		log("\n");
+		log("This command renames cell parameters and/or mapps key/value pairs to\n");
+		log("other key/value pairs.\n");
+		log("\n");
+		log_attrmap_paramap_options();
+		log("\n");
+		log("For example, mapping Diamond-style ECP5 \"init\" attributes to Yosys-style:\n");
+		log("\n");
+		log("    paramap -tocase INIT t:LUT4\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing PARAMAP pass (move or copy cell parameters).\n");
+
+		vector<std::unique_ptr<AttrmapAction>> actions;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (parse_attrmap_paramap_options(argidx, args, actions))
+				continue;
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		for (auto cell : module->selected_cells())
+			attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->parameters);
+	}
+} ParamapPass;
+
 PRIVATE_NAMESPACE_END

From 47ffbf554ef98a19222b42e48a9c58f3b55364fa Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 28 Aug 2019 10:06:42 +0200
Subject: [PATCH 097/111] Fix typo

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/techmap/attrmap.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
index 3a2835733..5f30817d4 100644
--- a/passes/techmap/attrmap.cc
+++ b/passes/techmap/attrmap.cc
@@ -227,7 +227,7 @@ struct AttrmapPass : public Pass {
 		log("\n");
 		log("    attrmap [options] [selection]\n");
 		log("\n");
-		log("This command renames attributes and/or mapps key/value pairs to\n");
+		log("This command renames attributes and/or maps key/value pairs to\n");
 		log("other key/value pairs.\n");
 		log("\n");
 		log_attrmap_paramap_options();
@@ -307,7 +307,7 @@ struct ParamapPass : public Pass {
 		log("\n");
 		log("    paramap [options] [selection]\n");
 		log("\n");
-		log("This command renames cell parameters and/or mapps key/value pairs to\n");
+		log("This command renames cell parameters and/or maps key/value pairs to\n");
 		log("other key/value pairs.\n");
 		log("\n");
 		log_attrmap_paramap_options();

From 9314a0a42ec05e82d2d3d77aebddfb06271a4730 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 10:51:39 -0700
Subject: [PATCH 098/111] Add (* clkbuf_sink *) to SRLC16E, reorder ports to
 match vendor

---
 techlibs/xilinx/cells_sim.v | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 973e17212..e12b77c02 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -380,9 +380,10 @@ endmodule
 
 module SRL16E (
   output Q,
+  input A0, A1, A2, A3, CE,
   (* clkbuf_sink *)
   input CLK,
-  input A0, A1, A2, A3, CE, D
+  input D
 );
   parameter [15:0] INIT = 16'h0000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -401,7 +402,10 @@ endmodule
 module SRLC16E (
   output Q,
   output Q15,
-  input A0, A1, A2, A3, CE, CLK, D
+  input A0, A1, A2, A3, CE,
+  (* clkbuf_sink *)
+  input CLK,
+  input D
 );
   parameter [15:0] INIT = 16'h0000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -422,9 +426,10 @@ module SRLC32E (
   output Q,
   output Q31,
   input [4:0] A,
+  input CE,
   (* clkbuf_sink *)
   input CLK,
-  input CE, D
+  input D
 );
   parameter [31:0] INIT = 32'h00000000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;

From 129df7184a2b85553366f9d56e26ac4eaccc5a52 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:07:07 -0700
Subject: [PATCH 099/111] Update to new $__ICE40_CARRY_WRAPPER

---
 techlibs/ice40/cells_sim.v | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index c7f3bdad2..02726605f 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -142,15 +142,16 @@ module SB_CARRY (output CO, input I0, I1, CI);
 endmodule
 
 (* abc_box_id = 1, lib_whitebox *)
-module \$__ICE40_FULL_ADDER (
+module \$__ICE40_CARRY_WRAPPER (
 	(* abc_carry *)
 	output CO,
 	output O,
-	input A,
-	input B,
+	input A, B,
 	(* abc_carry *)
-	input CI
+	input CI,
+	input I0, I3,
 );
+	parameter LUT = 0;
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),
@@ -158,16 +159,12 @@ module \$__ICE40_FULL_ADDER (
 		.CO(CO)
 	);
 	SB_LUT4 #(
-		//         I0: 1010 1010 1010 1010
-		//         I1: 1100 1100 1100 1100
-		//         I2: 1111 0000 1111 0000
-		//         I3: 1111 1111 0000 0000
-		.LUT_INIT(16'b 0110_1001_1001_0110)
+		.LUT_INIT(LUT)
 	) adder (
-		.I0(1'b0),
+		.I0(I0),
 		.I1(A),
 		.I2(B),
-		.I3(CI),
+		.I3(I3),
 		.O(O)
 	);
 endmodule

From 077e9d4ada7fbc75ab87fe7f390d58e2d53b4472 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:07:24 -0700
Subject: [PATCH 100/111] Update box size and timings

---
 techlibs/ice40/abc_hx.box | 8 ++++----
 techlibs/ice40/abc_lp.box | 8 ++++----
 techlibs/ice40/abc_u.box  | 8 ++++----
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index c0ea742e2..571152129 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -3,11 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
 # Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-400 379 316
-259 231 126
+$__ICE40_FULL_ADDER 1 1 5 2
+400 379 449 316 316
+259 231 -   -   126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index d73b6d649..a9f8699fc 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -3,11 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
 # Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-589 558 465
-675 609 186 
+$__ICE40_FULL_ADDER 1 1 5 2
+589 558 661 465 465
+675 609 -   -   186
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 42d666051..bc8a8d9cd 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -3,11 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
 # Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-1231 1205 874
-675  609  278
+$__ICE40_FULL_ADDER 1 1 5 2
+1231 1205 1285 874 874
+675  609  -    -   278

From 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:07:36 -0700
Subject: [PATCH 101/111] Remove $__ICE40_FULL_ADDER handling from ice40_opt;
 cannot reason with

CARRY_WRAPPER in the same way since I0 and I3 could be used
---
 techlibs/ice40/ice40_opt.cc | 45 -------------------------------------
 1 file changed, 45 deletions(-)

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index d5106b805..f528607d6 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,51 +83,6 @@ static void run_ice40_opts(Module *module)
 			}
 			continue;
 		}
-
-		if (cell->type == "$__ICE40_FULL_ADDER")
-		{
-			SigSpec non_const_inputs, replacement_output;
-			int count_zeros = 0, count_ones = 0;
-
-			SigBit inbit[3] = {
-				cell->getPort("\\A"),
-				cell->getPort("\\B"),
-				cell->getPort("\\CI")
-			};
-			for (int i = 0; i < 3; i++)
-				if (inbit[i].wire == nullptr) {
-					if (inbit[i] == State::S1)
-						count_ones++;
-					else
-						count_zeros++;
-				} else
-					non_const_inputs.append(inbit[i]);
-
-			if (count_zeros >= 2)
-				replacement_output = State::S0;
-			else if (count_ones >= 2)
-				replacement_output = State::S1;
-			else if (GetSize(non_const_inputs) == 1)
-				replacement_output = non_const_inputs;
-
-			if (GetSize(replacement_output)) {
-				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
-				module->connect(cell->getPort("\\CO")[0], replacement_output);
-				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
-						log_id(module), log_id(cell), log_signal(replacement_output));
-				cell->type = "$lut";
-				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
-				cell->setPort("\\Y", cell->getPort("\\O"));
-				cell->unsetPort("\\B");
-				cell->unsetPort("\\CI");
-				cell->unsetPort("\\CO");
-				cell->unsetPort("\\O");
-				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
-				cell->setParam("\\WIDTH", 4);
-			}
-			continue;
-		}
 	}
 
 	for (auto cell : sb_lut_cells)

From e569f138704a28654cc52c917bba4decffa29f54 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:22:44 -0700
Subject: [PATCH 102/111] Revert "Remove $__ICE40_FULL_ADDER handling from
 ice40_opt; cannot reason with"

This reverts commit 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f.
---
 techlibs/ice40/ice40_opt.cc | 45 +++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index f528607d6..d5106b805 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,6 +83,51 @@ static void run_ice40_opts(Module *module)
 			}
 			continue;
 		}
+
+		if (cell->type == "$__ICE40_FULL_ADDER")
+		{
+			SigSpec non_const_inputs, replacement_output;
+			int count_zeros = 0, count_ones = 0;
+
+			SigBit inbit[3] = {
+				cell->getPort("\\A"),
+				cell->getPort("\\B"),
+				cell->getPort("\\CI")
+			};
+			for (int i = 0; i < 3; i++)
+				if (inbit[i].wire == nullptr) {
+					if (inbit[i] == State::S1)
+						count_ones++;
+					else
+						count_zeros++;
+				} else
+					non_const_inputs.append(inbit[i]);
+
+			if (count_zeros >= 2)
+				replacement_output = State::S0;
+			else if (count_ones >= 2)
+				replacement_output = State::S1;
+			else if (GetSize(non_const_inputs) == 1)
+				replacement_output = non_const_inputs;
+
+			if (GetSize(replacement_output)) {
+				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+				module->connect(cell->getPort("\\CO")[0], replacement_output);
+				module->design->scratchpad_set_bool("opt.did_something", true);
+				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
+						log_id(module), log_id(cell), log_signal(replacement_output));
+				cell->type = "$lut";
+				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\Y", cell->getPort("\\O"));
+				cell->unsetPort("\\B");
+				cell->unsetPort("\\CI");
+				cell->unsetPort("\\CO");
+				cell->unsetPort("\\O");
+				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
+				cell->setParam("\\WIDTH", 4);
+			}
+			continue;
+		}
 	}
 
 	for (auto cell : sb_lut_cells)

From f5b4bc847c02d6c3e06c086a1375840ccac936cd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:25:05 -0700
Subject: [PATCH 103/111] Adapt to $__ICE40_CARRY_WRAPPER

---
 techlibs/ice40/ice40_opt.cc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index d5106b805..58f106f7c 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type == "$__ICE40_FULL_ADDER")
+		if (cell->type == "$__ICE40_CARRY_WRAPPER")
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
@@ -114,13 +114,15 @@ static void run_ice40_opts(Module *module)
 				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
 				module->connect(cell->getPort("\\CO")[0], replacement_output);
 				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
+				log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
-				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
 				cell->setPort("\\Y", cell->getPort("\\O"));
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
+				cell->unsetPort("\\I0");
+				cell->unsetPort("\\I3");
 				cell->unsetPort("\\CO");
 				cell->unsetPort("\\O");
 				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));

From d46d38e4d5e1502ea5cb6075161c87bd837af9eb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:25:54 -0700
Subject: [PATCH 104/111] Trailing comma

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 02726605f..2a7487f6b 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -149,7 +149,7 @@ module \$__ICE40_CARRY_WRAPPER (
 	input A, B,
 	(* abc_carry *)
 	input CI,
-	input I0, I3,
+	input I0, I3
 );
 	parameter LUT = 0;
 	SB_CARRY carry (

From dd42aa87b9b3bb041cbfe49079c6538f0a6d5646 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:34:32 -0700
Subject: [PATCH 105/111] Add ice40_opt test

---
 tests/ice40/ice40_opt.ys | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 tests/ice40/ice40_opt.ys

diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys
new file mode 100644
index 000000000..18e0d2b8a
--- /dev/null
+++ b/tests/ice40/ice40_opt.ys
@@ -0,0 +1,24 @@
+read_verilog -icells -formal <<EOT
+module top(input CI, I0, output CO, O);
+    wire A = 1'b0, B = 1'b0;
+	\$__ICE40_CARRY_WRAPPER #(
+		//    A[0]: 1010 1010 1010 1010
+		//    A[1]: 1100 1100 1100 1100
+		//    A[2]: 1111 0000 1111 0000
+		//    A[3]: 1111 1111 0000 0000
+		.LUT(~16'b 0110_1001_1001_0110)
+	) fadd (
+		.A(A),
+		.B(B),
+		.CI(CI),
+		.I0(I0),
+		.I3(CI),
+		.CO(CO),
+		.O(O)
+	);
+endmodule
+EOT
+
+equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
+design -load postopt
+select -assert-count 1 t:$lut

From e301a3dadbc81a300443713cf7877ea24cc0b2b2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:44:57 -0700
Subject: [PATCH 106/111] Add SB_CARRY to ice40_opt test

---
 tests/ice40/ice40_opt.ys | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys
index 18e0d2b8a..b17c69c91 100644
--- a/tests/ice40/ice40_opt.ys
+++ b/tests/ice40/ice40_opt.ys
@@ -1,5 +1,5 @@
 read_verilog -icells -formal <<EOT
-module top(input CI, I0, output CO, O);
+module top(input CI, I0, output [1:0] CO, output O);
     wire A = 1'b0, B = 1'b0;
 	\$__ICE40_CARRY_WRAPPER #(
 		//    A[0]: 1010 1010 1010 1010
@@ -7,18 +7,20 @@ module top(input CI, I0, output CO, O);
 		//    A[2]: 1111 0000 1111 0000
 		//    A[3]: 1111 1111 0000 0000
 		.LUT(~16'b 0110_1001_1001_0110)
-	) fadd (
+	) u0 (
 		.A(A),
 		.B(B),
 		.CI(CI),
 		.I0(I0),
 		.I3(CI),
-		.CO(CO),
+		.CO(CO[0]),
 		.O(O)
 	);
+    SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
 endmodule
 EOT
 
 equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
+select -assert-count 1 t:*
 select -assert-count 1 t:$lut

From a4f641f2303bc6f04751a15ec49cf2658ea8eb63 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:45:09 -0700
Subject: [PATCH 107/111] Do not overwrite LUT param

---
 techlibs/ice40/ice40_opt.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 58f106f7c..ea56d3f4d 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -125,7 +125,6 @@ static void run_ice40_opts(Module *module)
 				cell->unsetPort("\\I3");
 				cell->unsetPort("\\CO");
 				cell->unsetPort("\\O");
-				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
 				cell->setParam("\\WIDTH", 4);
 			}
 			continue;

From 13ecd8b0df267285eb9f0a6fda84684ef491eded Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:47:48 -0700
Subject: [PATCH 108/111] Add run-test.sh too

---
 tests/ice40/run-test.sh | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100755 tests/ice40/run-test.sh

diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh
new file mode 100755
index 000000000..ea56b70f0
--- /dev/null
+++ b/tests/ice40/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk

From 89695fd3ab488f7c6e32347ebfb29e15d8ba271e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 29 Aug 2019 12:05:26 +0200
Subject: [PATCH 109/111] Bump YOSYS_VER

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index e56db424d..692b19826 100644
--- a/Makefile
+++ b/Makefile
@@ -115,7 +115,7 @@ LDFLAGS += -rdynamic
 LDLIBS += -lrt
 endif
 
-YOSYS_VER := 0.9+1
+YOSYS_VER := 0.9+36
 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o
 

From 25b1670a8425198abfcef4602a3d1ddcc0ca5d40 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 29 Aug 2019 07:03:32 -0700
Subject: [PATCH 110/111] Rename boxes too

---
 techlibs/ice40/abc_hx.box | 2 +-
 techlibs/ice40/abc_lp.box | 2 +-
 techlibs/ice40/abc_u.box  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 571152129..3ea70bc91 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 5 2
+$__ICE40_CARRY_WRAPPER 1 1 5 2
 400 379 449 316 316
 259 231 -   -   126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index a9f8699fc..473e92fe9 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 5 2
+$__ICE40_CARRY_WRAPPER 1 1 5 2
 589 558 661 465 465
 675 609 -   -   186
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index bc8a8d9cd..f00e247b8 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 5 2
+$__ICE40_CARRY_WRAPPER 1 1 5 2
 1231 1205 1285 874 874
 675  609  -    -   278

From 14677610602ee18bcf1a41a0c54a626965e6bb06 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 29 Aug 2019 10:33:28 -0700
Subject: [PATCH 111/111] Fix typo that's gone unnoticed for 5 months!?!

---
 passes/techmap/shregmap.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 5e298d8dd..02cc27ae2 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -346,7 +346,7 @@ struct ShregmapWorker
 				IdString q_port = opts.ffcells.at(c1->type).second;
 
 				auto c1_conn = c1->connections();
-				auto c2_conn = c1->connections();
+				auto c2_conn = c2->connections();
 
 				c1_conn.erase(d_port);
 				c1_conn.erase(q_port);