mirror of https://github.com/YosysHQ/yosys.git
fsm_extract: avoid calling log_signal to determine wire name
log_signal can result in a string with spaces (when bit selection is involved), which breaks the rule of IdString not containing whitespace. Instead, remove the sigspec from the name entirely — given that the resulting wire will have no users, it will be removed later anyway, so its name doesn't really matter. Fixes #2118
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@ -394,7 +394,7 @@ static void extract_fsm(RTLIL::Wire *wire)
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RTLIL::Cell *cell = module->cells_.at(cellport.first);
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RTLIL::Cell *cell = module->cells_.at(cellport.first);
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RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second));
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RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second));
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RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
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RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
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RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), autoidx++), unconn_sig.size());
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RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%d", autoidx++), unconn_sig.size());
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port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
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port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
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}
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}
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}
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}
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