riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Removed SystemVerilog module end label

This commit is contained in:
Richard Herveille 2024-03-19 01:31:36 +01:00
parent 7647eb70a6
commit 2893938355
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/intel/max10/cells_sim.v
View File

@ -322,7 +322,7 @@ module fiftyfivenm_mac_mult (
input aclr;
input clk;
input ena;
endmodule : fiftyfivenm_mac_mult
endmodule //fiftyfivenm_mac_mult
module fiftyfivenm_mac_out (
dataa,
@ -342,4 +342,4 @@ module fiftyfivenm_mac_out (
input aclr;
input clk;
input ena;
endmodule : fiftyfivenm_mac_out
endmodule //fiftyfivenm_mac_out