riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed typo in help text

This commit is contained in:
Andrew Zonenberg 2016-04-22 23:01:39 -07:00
parent 0cbe70eaa4
commit 2849fd486e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/techmap/shregmap.cc
View File

@ -377,7 +377,7 @@ struct ShregmapPass : public Pass {
log("\n"); log("\n");
log(" shregmap [options] [selection]\n"); log(" shregmap [options] [selection]\n");
log("\n"); log("\n");
log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register.\n"); log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n"); log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n"); log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n"); log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");