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Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup 

frontend: cleanup to use more ID::*, more dict<> instead of map<>
This commit is contained in:
Eddie Hung 2020-05-05 07:59:40 -07:00 committed by GitHub
parent ae409d4d81 22bf22fab4
commit 283b1130a6
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GPG Key ID: 4AEE18F83AFDEB23
7 changed files with 34 additions and 31 deletions
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2
frontends/ast/genrtlil.cc
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@ -171,7 +171,7 @@ struct AST_INTERNAL::LookaheadRewriter
for (auto c : node->id2ast->children) for (auto c : node->id2ast->children)
wire->children.push_back(c->clone()); wire->children.push_back(c->clone());
wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++); wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++);
wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
wire->is_logic = true; wire->is_logic = true;
while (wire->simplify(true, false, false, 1, -1, false, false)) { } while (wire->simplify(true, false, false, 1, -1, false, false)) { }
current_ast_mod->children.push_back(wire); current_ast_mod->children.push_back(wire);

24
frontends/ast/simplify.cc
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@ -920,11 +920,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
range_swapped = templ->range_swapped; range_swapped = templ->range_swapped;
range_left = templ->range_left; range_left = templ->range_left;
range_right = templ->range_right; range_right = templ->range_right;
attributes["\\wiretype"] = mkconst_str(resolved_type->str); attributes[ID::wiretype] = mkconst_str(resolved_type->str);
//check if enum //check if enum
if (templ->attributes.count("\\enum_type")){ if (templ->attributes.count(ID::enum_type)){
//get reference to enum node: //get reference to enum node:
std::string enum_type = templ->attributes["\\enum_type"]->str.c_str(); const std::string &enum_type = templ->attributes[ID::enum_type]->str;
// log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type)); // log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type));
// log("current scope:\n"); // log("current scope:\n");
// for (auto &it : current_scope) // for (auto &it : current_scope)
@ -972,7 +972,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed); RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed);
enum_item_str.append(val.as_string()); enum_item_str.append(val.as_string());
//set attribute for available val to enum item name mappings //set attribute for available val to enum item name mappings
attributes[enum_item_str.c_str()] = mkconst_str(enum_item->str); attributes[enum_item_str] = mkconst_str(enum_item->str);
} }
} }
@ -1021,7 +1021,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
range_swapped = templ->range_swapped; range_swapped = templ->range_swapped;
range_left = templ->range_left; range_left = templ->range_left;
range_right = templ->range_right; range_right = templ->range_right;
attributes["\\wiretype"] = mkconst_str(resolved_type->str); attributes[ID::wiretype] = mkconst_str(resolved_type->str);
for (auto template_child : templ->children) for (auto template_child : templ->children)
children.push_back(template_child->clone()); children.push_back(template_child->clone());
did_something = true; did_something = true;
@ -1812,14 +1812,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true))); AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", filename.c_str(), location.first_line, autoidx++); wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
wire_mask->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire_mask->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
wire_mask->is_logic = true; wire_mask->is_logic = true;
while (wire_mask->simplify(true, false, false, 1, -1, false, false)) { } while (wire_mask->simplify(true, false, false, 1, -1, false, false)) { }
current_ast_mod->children.push_back(wire_mask); current_ast_mod->children.push_back(wire_mask);
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true))); AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", filename.c_str(), location.first_line, autoidx++); wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
wire_data->is_logic = true; wire_data->is_logic = true;
while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
current_ast_mod->children.push_back(wire_data); current_ast_mod->children.push_back(wire_data);
@ -2639,7 +2639,7 @@ skip_dynamic_range_lvalue_expansion:;
bool recommend_const_eval = false; bool recommend_const_eval = false;
bool require_const_eval = in_param ? false : has_const_only_constructs(recommend_const_eval); bool require_const_eval = in_param ? false : has_const_only_constructs(recommend_const_eval);
if ((in_param || recommend_const_eval || require_const_eval) && !decl->attributes.count("\\via_celltype")) if ((in_param || recommend_const_eval || require_const_eval) && !decl->attributes.count(ID::via_celltype))
{ {
bool all_args_const = true; bool all_args_const = true;
for (auto child : children) { for (auto child : children) {
@ -2698,9 +2698,9 @@ skip_dynamic_range_lvalue_expansion:;
goto replace_fcall_with_id; goto replace_fcall_with_id;
} }
if (decl->attributes.count("\\via_celltype")) if (decl->attributes.count(ID::via_celltype))
{ {
std::string celltype = decl->attributes.at("\\via_celltype")->asAttrConst().decode_string(); std::string celltype = decl->attributes.at(ID::via_celltype)->asAttrConst().decode_string();
std::string outport = str; std::string outport = str;
if (celltype.find(' ') != std::string::npos) { if (celltype.find(' ') != std::string::npos) {
@ -2794,7 +2794,7 @@ skip_dynamic_range_lvalue_expansion:;
wire->is_reg = true; wire->is_reg = true;
wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
if (child->type == AST_ENUM_ITEM) if (child->type == AST_ENUM_ITEM)
wire->attributes["\\enum_base_type"] = child->attributes["\\enum_base_type"]; wire->attributes[ID::enum_base_type] = child->attributes[ID::enum_base_type];
wire_cache[child->str] = wire; wire_cache[child->str] = wire;
@ -4094,7 +4094,7 @@ void AstNode::allocateDefaultEnumValues()
int last_enum_int = -1; int last_enum_int = -1;
for (auto node : children) { for (auto node : children) {
log_assert(node->type==AST_ENUM_ITEM); log_assert(node->type==AST_ENUM_ITEM);
node->attributes["\\enum_base_type"] = mkconst_str(str); node->attributes[ID::enum_base_type] = mkconst_str(str);
for (size_t i = 0; i < node->children.size(); i++) { for (size_t i = 0; i < node->children.size(); i++) {
switch (node->children[i]->type) { switch (node->children[i]->type) {
case AST_NONE: case AST_NONE:

6
frontends/ilang/ilang_parser.y
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@ -107,16 +107,16 @@ module:
delete_current_module = false; delete_current_module = false;
if (current_design->has($2)) { if (current_design->has($2)) {
RTLIL::Module *existing_mod = current_design->module($2); RTLIL::Module *existing_mod = current_design->module($2);
if (!flag_overwrite && (flag_lib || (attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()))) { if (!flag_overwrite && (flag_lib || (attrbuf.count(ID::blackbox) && attrbuf.at(ID::blackbox).as_bool()))) {
log("Ignoring blackbox re-definition of module %s.\n", $2); log("Ignoring blackbox re-definition of module %s.\n", $2);
delete_current_module = true; delete_current_module = true;
} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { } else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str()); rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
} else if (flag_nooverwrite) { } else if (flag_nooverwrite) {
log("Ignoring re-definition of module %s.\n", $2); log("Ignoring re-definition of module %s.\n", $2);
delete_current_module = true; delete_current_module = true;
} else { } else {
log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", $2); log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", $2);
current_design->remove(existing_mod); current_design->remove(existing_mod);
} }
} }

2
frontends/verilog/verilog_frontend.cc
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@ -48,7 +48,7 @@ static void error_on_dpi_function(AST::AstNode *node)
error_on_dpi_function(child); error_on_dpi_function(child);
} }
static void add_package_types(std::map<std::string, AST::AstNode *> &user_types, std::vector<AST::AstNode *> &package_list) static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std::vector<AST::AstNode *> &package_list)
{ {
// prime the parser's user type lookup table with the package qualified names // prime the parser's user type lookup table with the package qualified names
// of typedefed names in the packages seen so far. // of typedefed names in the packages seen so far.

2
frontends/verilog/verilog_frontend.h
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@ -50,7 +50,7 @@ namespace VERILOG_FRONTEND
extern std::vector<UserTypeMap *> user_type_stack; extern std::vector<UserTypeMap *> user_type_stack;
// names of package typedef'ed types // names of package typedef'ed types
extern std::map<std::string, AST::AstNode*> pkg_user_types; extern dict<std::string, AST::AstNode*> pkg_user_types;
// state of `default_nettype // state of `default_nettype
extern bool default_nettype_wire; extern bool default_nettype_wire;

26
frontends/verilog/verilog_parser.y
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@ -50,12 +50,12 @@ using namespace VERILOG_FRONTEND;
YOSYS_NAMESPACE_BEGIN YOSYS_NAMESPACE_BEGIN
namespace VERILOG_FRONTEND { namespace VERILOG_FRONTEND {
int port_counter; int port_counter;
std::map<std::string, int> port_stubs; dict<std::string, int> port_stubs;
std::map<std::string, AstNode*> *attr_list, default_attr_list; dict<IdString, AstNode*> *attr_list, default_attr_list;
std::stack<std::map<std::string, AstNode*> *> attr_list_stack; std::stack<dict<IdString, AstNode*> *> attr_list_stack;
std::map<std::string, AstNode*> *albuf; dict<IdString, AstNode*> *albuf;
std::vector<UserTypeMap*> user_type_stack; std::vector<UserTypeMap*> user_type_stack;
std::map<std::string, AstNode*> pkg_user_types; dict<std::string, AstNode*> pkg_user_types;
std::vector<AstNode*> ast_stack; std::vector<AstNode*> ast_stack;
struct AstNode *astbuf1, *astbuf2, *astbuf3; struct AstNode *astbuf1, *astbuf2, *astbuf3;
struct AstNode *current_function_or_task; struct AstNode *current_function_or_task;
@ -87,7 +87,7 @@ YOSYS_NAMESPACE_END
int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param); int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al) static void append_attr(AstNode *ast, dict<IdString, AstNode*> *al)
{ {
for (auto &it : *al) { for (auto &it : *al) {
if (ast->attributes.count(it.first) > 0) if (ast->attributes.count(it.first) > 0)
@ -97,7 +97,7 @@ static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
delete al; delete al;
} }
static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al) static void append_attr_clone(AstNode *ast, dict<IdString, AstNode*> *al)
{ {
for (auto &it : *al) { for (auto &it : *al) {
if (ast->attributes.count(it.first) > 0) if (ast->attributes.count(it.first) > 0)
@ -106,7 +106,7 @@ static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al)
} }
} }
static void free_attr(std::map<std::string, AstNode*> *al) static void free_attr(dict<IdString, AstNode*> *al)
{ {
for (auto &it : *al) for (auto &it : *al)
delete it.second; delete it.second;
@ -192,7 +192,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
%union { %union {
std::string *string; std::string *string;
struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast; struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al; YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
struct specify_target *specify_target_ptr; struct specify_target *specify_target_ptr;
struct specify_triple *specify_triple_ptr; struct specify_triple *specify_triple_ptr;
struct specify_rise_fall *specify_rise_fall_ptr; struct specify_rise_fall *specify_rise_fall_ptr;
@ -289,7 +289,7 @@ attr:
{ {
if (attr_list != nullptr) if (attr_list != nullptr)
attr_list_stack.push(attr_list); attr_list_stack.push(attr_list);
attr_list = new std::map<std::string, AstNode*>; attr_list = new dict<IdString, AstNode*>;
for (auto &it : default_attr_list) for (auto &it : default_attr_list)
(*attr_list)[it.first] = it.second->clone(); (*attr_list)[it.first] = it.second->clone();
} attr_opt { } attr_opt {
@ -311,7 +311,7 @@ defattr:
DEFATTR_BEGIN { DEFATTR_BEGIN {
if (attr_list != nullptr) if (attr_list != nullptr)
attr_list_stack.push(attr_list); attr_list_stack.push(attr_list);
attr_list = new std::map<std::string, AstNode*>; attr_list = new dict<IdString, AstNode*>;
for (auto &it : default_attr_list) for (auto &it : default_attr_list)
delete it.second; delete it.second;
default_attr_list.clear(); default_attr_list.clear();
@ -1390,7 +1390,7 @@ enum_type: TOK_ENUM {
delete astbuf1; delete astbuf1;
astbuf1 = tnode; astbuf1 = tnode;
tnode->type = AST_WIRE; tnode->type = AST_WIRE;
tnode->attributes["\\enum_type"] = AstNode::mkconst_str(astbuf2->str); tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
// drop constant but keep any range // drop constant but keep any range
delete tnode->children[0]; delete tnode->children[0];
tnode->children.erase(tnode->children.begin()); } tnode->children.erase(tnode->children.begin()); }
@ -2345,7 +2345,7 @@ unique_case_attr:
case_attr: case_attr:
attr unique_case_attr { attr unique_case_attr {
if ($2) (*$1)["\\parallel_case"] = AstNode::mkconst_int(1, false); if ($2) (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
$$ = $1; $$ = $1;
}; };

3
kernel/constids.inc
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@ -74,6 +74,8 @@ X(EN)
X(EN_DST) X(EN_DST)
X(EN_POLARITY) X(EN_POLARITY)
X(EN_SRC) X(EN_SRC)
X(enum_base_type)
X(enum_type)
X(equiv_merged) X(equiv_merged)
X(equiv_region) X(equiv_region)
X(extract_order) X(extract_order)
@ -196,6 +198,7 @@ X(U)
X(unique) X(unique)
X(unused_bits) X(unused_bits)
X(V) X(V)
X(via_celltype)
X(wand) X(wand)
X(whitebox) X(whitebox)
X(WIDTH) X(WIDTH)