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Wrong way around

This commit is contained in:
Eddie Hung 2019-08-10 11:55:00 -07:00
parent 02b0d328ad
commit 282cc77604
1 changed files with 2 additions and 2 deletions
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4
passes/opt/opt_expr.cc
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@ -659,7 +659,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
break; break;
} }
if (i > 0) { if (i > 0) {
cover("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort("\\A", sig_a.extract_end(i));
cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort("\\B", sig_b.extract_end(i));
cell->setPort("\\Y", sig_y.extract_end(i)); cell->setPort("\\Y", sig_y.extract_end(i));
@ -704,7 +704,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
break; break;
} }
if (i > 0) { if (i > 0) {
cover_list("opt.opt_expr.fine.$alu"); cover("opt.opt_expr.fine.$alu");
cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort("\\A", sig_a.extract_end(i));
cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort("\\B", sig_b.extract_end(i));
cell->setPort("\\X", sig_x.extract_end(i)); cell->setPort("\\X", sig_x.extract_end(i));