mirror of https://github.com/YosysHQ/yosys.git
Fix spacing in opt_share tests, change wording in opt_share help
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@ -2,6 +2,7 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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@ -308,17 +309,20 @@ void remove_multi_user_outbits(RTLIL::Module *module, dict<RTLIL::SigBit, RTLIL:
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}
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}
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struct OptRmdffPass : public Pass {
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OptRmdffPass() : Pass("opt_share", "merge arithmetic operators that share an operand") {}
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struct OptSharePass : public Pass {
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OptSharePass() : Pass("opt_share", "merge arithmetic operators that share an operand") {}
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_share [selection]\n");
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log("\n");
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log("This pass identifies arithmetic operators that share an operand and whose\n");
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log("results are used in mutually exclusive cases controlled by a multiplexer,\n");
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log("and merges them together by multiplexing the other operands.\n");
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log("This pass identifies mutually exclusive $alu arithmetic cells that:\n");
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log(" (a) share an input operand\n");
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log(" (b) drive the same $mux, $_MUX_, or $pmux multiplexing cell allowing\n");
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log(" the $alu cell to be merged and the multiplexer to be moved from\n");
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log(" multiplexing its output to multiplexing the non-shared input operands.\n");
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log("\n");
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}
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void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
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@ -454,6 +458,6 @@ struct OptRmdffPass : public Pass {
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}
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}
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} OptRmdffPass;
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} OptSharePass;
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PRIVATE_NAMESPACE_END
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@ -6,7 +6,6 @@ module opt_share_test(
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output reg signed [15:0] res
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);
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always @* begin
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case(sel)
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0: res = a + b;
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@ -6,7 +6,6 @@ module opt_share_test(
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output reg [31:0] res
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);
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always @* begin
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case(sel)
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0: res = {a + b, a};
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@ -7,7 +7,6 @@ module opt_share_test(
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output reg [15:0] res
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);
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always @* begin
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case(sel)
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0: res = a + d;
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@ -6,7 +6,6 @@ module opt_share_test(
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output reg [15:0] res
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);
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always @* begin
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case(sel)
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0: res = a + b;
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@ -6,7 +6,6 @@ module opt_share_test(
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output reg [15:0] res
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);
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always @* begin
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case(sel)
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0: res = a + b;
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