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Stop trying to be too smart by prematurely optimising

This commit is contained in:
Eddie Hung 2019-09-26 09:57:11 -07:00
parent 35aaa8d73a
commit 27e5bf5aad
3 changed files with 14 additions and 38 deletions
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36
techlibs/common/mul2dsp.v
View File

@ -146,17 +146,8 @@ module _80_mul (A, B, Y);
// reduction' approach also exists...
if (i == 0)
assign partial_sum[i] = partial[i];
else begin
// Rewrite the following statement explicitly in order
// to save on a call to 'opt_expr -fine' which would
// optimise away the '<<' op and trim size of adder
//assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
if (A_SIGNED && B_SIGNED)
assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]);
else
assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)];
assign partial_sum[i][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
end
assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];
end
\$__mul #(
@ -170,12 +161,7 @@ module _80_mul (A, B, Y);
.B(B),
.Y(last_partial)
);
//assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
if (A_SIGNED && B_SIGNED)
assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]);
else
assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)];
assign partial_sum[n][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];
assign Y = partial_sum[n];
end
else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
@ -211,17 +197,8 @@ module _80_mul (A, B, Y);
// reduction' approach also exists...
if (i == 0)
assign partial_sum[i] = partial[i];
else begin
// Rewrite the following statement explicitly in order
// to save on a call to 'opt_expr -fine' which would
// optimise away the '<<' op and trim size of adder
//assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
if (A_SIGNED && B_SIGNED)
assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]);
else
assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)];
assign partial_sum[i][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
end
assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1];
end
\$__mul #(
@ -235,12 +212,7 @@ module _80_mul (A, B, Y);
.B(B[B_WIDTH-1 -: last_B_WIDTH]),
.Y(last_partial)
);
//assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
if (A_SIGNED && B_SIGNED)
assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]);
else
assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)];
assign partial_sum[n][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0];
assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1];
assign Y = partial_sum[n];
end
else begin

6
techlibs/ice40/synth_ice40.cc
View File

@ -276,9 +276,11 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
run("wreduce t:$add", " (if -dsp)");
run("opt_expr -fine a:mul2dsp", " (if -dsp)");
run("wreduce a:mul2dsp", " (if -dsp)");
run("ice40_dsp", " (if -dsp)");
run("chtype -set $mul t:$__soft_mul","(if -dsp)");
run("setattr -unset mul2dsp a:mul2dsp", "(if -dsp)");
run("chtype -set $mul t:$__soft_mul", " (if -dsp)");
}
run("alumacc");
run("opt");

4
techlibs/xilinx/synth_xilinx.cc
View File

@ -346,7 +346,9 @@ struct SynthXilinxPass : public ScriptPass
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
run("wreduce t:$add");
run("opt_expr -fine a:mul2dsp");
run("wreduce a:mul2dsp");
run("setattr -unset mul2dsp a:mul2dsp");
run("xilinx_dsp");
run("chtype -set $mul t:$__soft_mul");
}