riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Proper example code

This commit is contained in:
Miodrag Milanovic 2022-03-14 15:39:11 +01:00
parent a502570c25
commit 27c5bafc95
2 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tests/sat/grom_cpu.v
View File

@ -185,7 +185,7 @@ module grom_cpu(
`ifdef DISASSEMBLY `ifdef DISASSEMBLY
$display("INC R%d",IR[1:0]); $display("INC R%d",IR[1:0]);
`endif `endif
alu_op <= 4'b0001; // ALU_OP_ADD alu_op <= 4'b0000; // ALU_OP_ADD
end end
2'b01 : begin 2'b01 : begin
`ifdef DISASSEMBLY `ifdef DISASSEMBLY

2
tests/sat/ram_memory.v
View File

@ -27,6 +27,8 @@ module ram_memory(
store[256] <= 8'b11010001; // OUT [0],R1 store[256] <= 8'b11010001; // OUT [0],R1
store[257] <= 8'b00000000; // store[257] <= 8'b00000000; //
store[258] <= 8'b01111110; // RET store[258] <= 8'b01111110; // RET
store[512] <= 8'b00000000;
end end
always @(posedge clk) always @(posedge clk)