This commit is contained in:
tklam 2018-10-03 21:17:03 +08:00
commit 27c46d94e3
4 changed files with 12 additions and 7 deletions

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@ -985,7 +985,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
use_const_chunk:
if (children.size() != 0) {
log_assert(children[0]->type == AST_RANGE);
if (children[0]->type != AST_RANGE)
log_file_error(filename, linenum, "Single range expected.\n");
int source_width = id2ast->range_left - id2ast->range_right + 1;
int source_offset = id2ast->range_right;
if (!children[0]->range_valid) {

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@ -1781,7 +1781,7 @@ skip_dynamic_range_lvalue_expansion:;
if (GetSize(children) == 2)
{
AstNode *buf = children[1]->clone();
while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
while (buf->simplify(true, false, false, stage, -1, false, false)) { }
if (buf->type != AST_CONSTANT)
log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
@ -1836,7 +1836,7 @@ skip_dynamic_range_lvalue_expansion:;
goto apply_newNode;
}
if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell")
if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell" || str == "\\$changed")
{
if (GetSize(children) != 1)
log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
@ -1853,6 +1853,9 @@ skip_dynamic_range_lvalue_expansion:;
if (str == "\\$stable")
newNode = new AstNode(AST_EQ, past, present);
else if (str == "\\$changed")
newNode = new AstNode(AST_NE, past, present);
else if (str == "\\$rose")
newNode = new AstNode(AST_LOGIC_AND, new AstNode(AST_LOGIC_NOT, past), present);

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@ -5,11 +5,11 @@ vcxsrc="$1-$2"
yosysver="$2"
gitsha="$3"
rm -rf YosysVS-Tpl-v1.zip YosysVS
wget http://www.clifford.at/yosys/nogit/YosysVS-Tpl-v1.zip
rm -rf YosysVS-Tpl-v2.zip YosysVS
wget http://www.clifford.at/yosys/nogit/YosysVS-Tpl-v2.zip
unzip YosysVS-Tpl-v1.zip
rm -f YosysVS-Tpl-v1.zip
unzip YosysVS-Tpl-v2.zip
rm -f YosysVS-Tpl-v2.zip
mv YosysVS "$vcxsrc"
{

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@ -13,4 +13,5 @@ endbram
match $__TRELLIS_DPR16X4
make_outreg
min wports 1
endmatch