mirror of https://github.com/YosysHQ/yosys.git
Merge branch 'master' of https://github.com/YosysHQ/yosys
This commit is contained in:
commit
27c46d94e3
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@ -985,7 +985,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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use_const_chunk:
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if (children.size() != 0) {
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log_assert(children[0]->type == AST_RANGE);
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if (children[0]->type != AST_RANGE)
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log_file_error(filename, linenum, "Single range expected.\n");
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int source_width = id2ast->range_left - id2ast->range_right + 1;
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int source_offset = id2ast->range_right;
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if (!children[0]->range_valid) {
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@ -1781,7 +1781,7 @@ skip_dynamic_range_lvalue_expansion:;
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if (GetSize(children) == 2)
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{
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AstNode *buf = children[1]->clone();
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while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
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while (buf->simplify(true, false, false, stage, -1, false, false)) { }
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if (buf->type != AST_CONSTANT)
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log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
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@ -1836,7 +1836,7 @@ skip_dynamic_range_lvalue_expansion:;
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goto apply_newNode;
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}
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if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell")
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if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell" || str == "\\$changed")
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{
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if (GetSize(children) != 1)
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log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
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@ -1853,6 +1853,9 @@ skip_dynamic_range_lvalue_expansion:;
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if (str == "\\$stable")
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newNode = new AstNode(AST_EQ, past, present);
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else if (str == "\\$changed")
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newNode = new AstNode(AST_NE, past, present);
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else if (str == "\\$rose")
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newNode = new AstNode(AST_LOGIC_AND, new AstNode(AST_LOGIC_NOT, past), present);
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@ -5,11 +5,11 @@ vcxsrc="$1-$2"
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yosysver="$2"
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gitsha="$3"
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rm -rf YosysVS-Tpl-v1.zip YosysVS
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wget http://www.clifford.at/yosys/nogit/YosysVS-Tpl-v1.zip
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rm -rf YosysVS-Tpl-v2.zip YosysVS
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wget http://www.clifford.at/yosys/nogit/YosysVS-Tpl-v2.zip
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unzip YosysVS-Tpl-v1.zip
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rm -f YosysVS-Tpl-v1.zip
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unzip YosysVS-Tpl-v2.zip
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rm -f YosysVS-Tpl-v2.zip
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mv YosysVS "$vcxsrc"
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{
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@ -13,4 +13,5 @@ endbram
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match $__TRELLIS_DPR16X4
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make_outreg
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min wports 1
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endmatch
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