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abstract: rework -init without bufnorm, with logging

This commit is contained in:
Emil J. Tywoniak 2025-02-10 14:56:52 +01:00
parent 78c5be1990
commit 27928f74ac
1 changed files with 17 additions and 14 deletions
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31
passes/cmds/abstract.cc
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@ -1,6 +1,7 @@
#include "kernel/yosys.h" #include "kernel/yosys.h"
#include "kernel/celltypes.h" #include "kernel/celltypes.h"
#include "kernel/ff.h" #include "kernel/ff.h"
#include "kernel/ffinit.h"
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
@ -160,22 +161,24 @@ unsigned int abstract_value(Module* mod, EnableLogic enable) {
} }
unsigned int abstract_init(Module* mod) { unsigned int abstract_init(Module* mod) {
// AbstractPortCtx ctx {mod, SigMap(mod), {}};
// collect_selected_ports(ctx);
unsigned int changed = 0; unsigned int changed = 0;
FfInitVals initvals;
SigMap sigmap(mod);
initvals.set(&sigmap, mod);
for (auto wire : mod->selected_wires())
for (auto bit : SigSpec(wire)) {
// TODO these don't seem too informative
log_debug("Removing init bit on %s due to selected wire %s\n", log_signal(bit), wire->name.c_str());
initvals.remove_init(bit);
}
// for (auto [cell, port] : ctx.outs) { for (auto cell : mod->selected_cells())
// SigSpec sig = cell->getPort(port); for (auto conn : cell->connections())
// log_assert(sig.is_wire()); if (cell->output(conn.first))
// if (!sig.as_wire()->has_attribute(ID::init)) for (auto bit : conn.second.bits()) {
// continue; log_debug("Removing init bit on %s due to selected cell %s\n", log_signal(bit), cell->name.c_str());
initvals.remove_init(bit);
// Const init = sig.as_wire()->attributes.at(ID::init); }
// sig.as_wire()->attributes.erase(ID::init);
// changed += sig.size();
// }
log_cmd_error("Not implemented\n"); (void)mod;
return changed; return changed;
} }