From edc378072301dba7ee79dd1d64a825faf72a1d62 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 17:20:12 -0700 Subject: [PATCH 1/4] techmap wires named _TECHMAP_REPLACE_. to create alias --- passes/techmap/techmap.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 08a1af2d5..8f8cff9fa 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -257,6 +257,12 @@ struct TechmapWorker w->add_strpool_attribute(ID(src), extra_src_attrs); } design->select(module, w); + + if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) { + IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_")); + Wire *replace_w = module->addWire(replace_name, it.second); + module->connect(replace_w, w); + } } SigMap tpl_sigmap(tpl); @@ -1198,6 +1204,10 @@ struct TechmapPass : public Pass { log("\n"); log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n"); log("and attributes of the cell that is being replaced.\n"); + log("A wire with a name of the form `_TECHMAP_REPLACE_.` in the map file will\n"); + log("cause a new wire alias to be created with its name set to the original but with\n"); + log("its `_TECHMAP_REPLACE_' prefix to be substituted with the name of the cell being\n"); + log("replaced.\n"); log("\n"); log("See 'help extract' for a pass that does the opposite thing.\n"); log("\n"); From 369652d4b99181e2f7b875b6c458c1a5a3b0381e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 17:20:39 -0700 Subject: [PATCH 2/4] Add test --- tests/techmap/techmap_replace.ys | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 tests/techmap/techmap_replace.ys diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys new file mode 100644 index 000000000..ee5c6bc7e --- /dev/null +++ b/tests/techmap/techmap_replace.ys @@ -0,0 +1,16 @@ +read_verilog < Date: Wed, 2 Oct 2019 12:43:18 -0700 Subject: [PATCH 3/4] Extend test with renaming cells with prefix too --- tests/techmap/techmap_replace.ys | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys index ee5c6bc7e..c2f42d50b 100644 --- a/tests/techmap/techmap_replace.ys +++ b/tests/techmap/techmap_replace.ys @@ -2,6 +2,7 @@ read_verilog < Date: Wed, 2 Oct 2019 12:43:35 -0700 Subject: [PATCH 4/4] Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf --- passes/techmap/techmap.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 8f8cff9fa..0c57733d4 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -384,6 +384,8 @@ struct TechmapWorker if (techmap_replace_cell) c_name = orig_cell_name; + else if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) + c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_")); else apply_prefix(cell->name, c_name); @@ -1204,10 +1206,12 @@ struct TechmapPass : public Pass { log("\n"); log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n"); log("and attributes of the cell that is being replaced.\n"); - log("A wire with a name of the form `_TECHMAP_REPLACE_.` in the map file will\n"); - log("cause a new wire alias to be created with its name set to the original but with\n"); - log("its `_TECHMAP_REPLACE_' prefix to be substituted with the name of the cell being\n"); - log("replaced.\n"); + log("A cell with a name of the form `_TECHMAP_REPLACE_.` in the map file will\n"); + log("be named thus but with the `_TECHMAP_REPLACE_' prefix substituted with the name\n"); + log("of the cell being replaced.\n"); + log("Similarly, a wire named in the form `_TECHMAP_REPLACE_.` will cause a\n"); + log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n"); + log("prefix also substituted.\n"); log("\n"); log("See 'help extract' for a pass that does the opposite thing.\n"); log("\n");