mirror of https://github.com/YosysHQ/yosys.git
Fixed RTLIL::SigSpec::append_bit() for appending constants
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274c514879
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@ -1716,9 +1716,10 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
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chunks.push_back(bit);
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else
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if (bit.wire == NULL)
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if (chunks.back().wire == NULL)
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if (chunks.back().wire == NULL) {
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chunks.back().data.bits.push_back(bit.data);
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else
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chunks.back().width++;
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} else
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chunks.push_back(bit);
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else
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if (chunks.back().wire == bit.wire && chunks.back().offset + chunks.back().width == bit.offset)
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