mirror of https://github.com/YosysHQ/yosys.git
verilog: strip leading and trailing spaces in macro args
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parent
98afe2b758
commit
27257a419f
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@ -390,12 +390,16 @@ static void input_file(std::istream &f, std::string filename)
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// the argument list); false if we finished with ','.
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static bool read_argument(std::string &dest)
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{
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skip_spaces();
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std::vector<char> openers;
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for (;;) {
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std::string tok = next_token(true);
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if (tok == ")") {
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if (openers.empty())
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if (openers.empty()) {
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while (dest.size() && (dest.back() == ' ' || dest.back() == '\t'))
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dest = dest.substr(0, dest.size() - 1);
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return true;
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}
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if (openers.back() != '(')
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log_error("Mismatched brackets in macro argument: %c and %c.\n",
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openers.back(), tok[0]);
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@ -0,0 +1,20 @@
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module top(
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IDENT_V_,
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IDENT_W_,
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IDENT_X_,
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IDENT_Y_,
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IDENT_Z_,
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IDENT_A_,
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IDENT_B_,
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IDENT_C_
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);
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`define MACRO(dummy, x) IDENT_``x``_
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output wire IDENT_V_;
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output wire `MACRO(_,W);
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output wire `MACRO(_, X);
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output wire `MACRO(_,Y );
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output wire `MACRO(_, Z );
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output wire `MACRO(_, A);
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output wire `MACRO(_,B );
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output wire `MACRO(_, C );
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endmodule
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