riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #4723 from povik/memv2-nordports 

rtlil: Adjust internal check for `$mem_v2` cells
This commit is contained in:
Martin Povišer 2024-11-18 15:44:39 +01:00 committed by GitHub
parent 1cb5fd08b7 e82e5f8b13
commit 270846a49a
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 12 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
kernel/rtlil.cc
View File

@ -1856,9 +1856,9 @@ namespace {
param_bits(ID::RD_COLLISION_X_MASK, max(1, param(ID::RD_PORTS) * param(ID::WR_PORTS)));
param_bits(ID::RD_WIDE_CONTINUATION, max(1, param(ID::RD_PORTS)));
param_bits(ID::RD_CE_OVER_SRST, max(1, param(ID::RD_PORTS)));
param_bits(ID::RD_ARST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
param_bits(ID::RD_SRST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
param_bits(ID::RD_INIT_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
param_bits(ID::RD_ARST_VALUE, max(1, param(ID::RD_PORTS) * param(ID::WIDTH)));
param_bits(ID::RD_SRST_VALUE, max(1, param(ID::RD_PORTS) * param(ID::WIDTH)));
param_bits(ID::RD_INIT_VALUE, max(1, param(ID::RD_PORTS) * param(ID::WIDTH)));
param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
param_bits(ID::WR_WIDE_CONTINUATION, max(1, param(ID::WR_PORTS)));

9
tests/memories/nordports.ys Normal file
View File

@ -0,0 +1,9 @@
# check memory_collect doesn't produce invalid RTLIL on a memory w/o read ports
read_rtlil <<EOF
autoidx 1
attribute \top 1
module \top
memory width 4 size 3 \foo
end
EOF
memory_collect