riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Cleanup

This commit is contained in:
Miodrag Milanovic 2022-01-31 12:00:15 +01:00
parent 6513300db7
commit 26de52fa09
2 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
kernel/fstdata.cc
View File

@ -43,7 +43,6 @@ FstData::FstData(std::string filename) : ctx(nullptr)
} }
} }
for (int i=0;i<zeros; i++) timescale_str += "0"; for (int i=0;i<zeros; i++) timescale_str += "0";
if (zeros>0)timescale_str += " ";
timescale_str += g_units[unit]; timescale_str += g_units[unit];
extractVarNames(); extractVarNames();
} }

2
passes/sat/sim.cc
View File

@ -1021,7 +1021,7 @@ struct SimWorker : SimShared
edges.erase(edges.begin() + (numcycles*2), edges.end()); edges.erase(edges.begin() + (numcycles*2), edges.end());
if ((startCount == stopCount) && writeback) { if ((startCount == stopCount) && writeback) {
log("Update initial state with values from %zu\n",startCount); log("Update initial state with values from [%zu%s]\n", startCount, fst->getTimescaleString());
if (edges.empty()) if (edges.empty())
edges.push_back(startCount); edges.push_back(startCount);
fst->reconstructAllAtTimes(edges); fst->reconstructAllAtTimes(edges);