mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #479 from Fatsie/latch_without_data
Some standard cell libraries include a latch with only set/reset.
This commit is contained in:
commit
26c4323d48
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@ -290,7 +290,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
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log_assert(!cell->type.empty());
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log_assert(!cell->type.empty());
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}
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}
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static void create_latch(RTLIL::Module *module, LibertyAst *node)
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static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_ignore_miss_data_latch)
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{
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{
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RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
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RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
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RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
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RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
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@ -309,8 +309,14 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
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preset_sig = parse_func_expr(module, child->value.c_str());
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preset_sig = parse_func_expr(module, child->value.c_str());
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}
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}
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if (enable_sig.size() == 0 || data_sig.size() == 0)
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if (enable_sig.size() == 0 || data_sig.size() == 0) {
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log_error("Latch cell %s has no data_in and/or enable attribute.\n", log_id(module->name));
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if (!flag_ignore_miss_data_latch)
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log_error("Latch cell %s has no data_in and/or enable attribute.\n", log_id(module->name));
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else
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log("Ignored latch cell %s with no data_in and/or enable attribute.\n", log_id(module->name));
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return false;
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}
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for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
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for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
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{
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{
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@ -399,6 +405,8 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
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cell->setPort("\\D", data_sig);
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cell->setPort("\\D", data_sig);
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cell->setPort("\\Q", iq_sig);
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cell->setPort("\\Q", iq_sig);
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cell->setPort("\\E", enable_sig);
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cell->setPort("\\E", enable_sig);
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return true;
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}
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}
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void parse_type_map(std::map<std::string, std::tuple<int, int, bool>> &type_map, LibertyAst *ast)
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void parse_type_map(std::map<std::string, std::tuple<int, int, bool>> &type_map, LibertyAst *ast)
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@ -466,6 +474,9 @@ struct LibertyFrontend : public Frontend {
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log(" ignore cells with a missing or invalid direction\n");
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log(" ignore cells with a missing or invalid direction\n");
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log(" specification on a pin\n");
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log(" specification on a pin\n");
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log("\n");
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log("\n");
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log(" -ignore_miss_data_latch\n");
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log(" ignore latches with missing data and/or enable pins\n");
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log("\n");
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log(" -setattr <attribute_name>\n");
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log(" -setattr <attribute_name>\n");
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log(" set the specified attribute (to the value 1) on all loaded modules\n");
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log(" set the specified attribute (to the value 1) on all loaded modules\n");
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log("\n");
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log("\n");
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@ -476,6 +487,7 @@ struct LibertyFrontend : public Frontend {
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bool flag_ignore_redef = false;
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bool flag_ignore_redef = false;
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bool flag_ignore_miss_func = false;
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bool flag_ignore_miss_func = false;
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bool flag_ignore_miss_dir = false;
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bool flag_ignore_miss_dir = false;
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bool flag_ignore_miss_data_latch = false;
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std::vector<std::string> attributes;
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std::vector<std::string> attributes;
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log_header(design, "Executing Liberty frontend.\n");
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log_header(design, "Executing Liberty frontend.\n");
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@ -499,6 +511,10 @@ struct LibertyFrontend : public Frontend {
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flag_ignore_miss_dir = true;
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flag_ignore_miss_dir = true;
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continue;
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continue;
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}
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}
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if (arg == "-ignore_miss_data_latch") {
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flag_ignore_miss_data_latch = true;
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continue;
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}
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if (arg == "-setattr" && argidx+1 < args.size()) {
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if (arg == "-setattr" && argidx+1 < args.size()) {
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attributes.push_back(RTLIL::escape_id(args[++argidx]));
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attributes.push_back(RTLIL::escape_id(args[++argidx]));
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continue;
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continue;
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@ -600,7 +616,10 @@ struct LibertyFrontend : public Frontend {
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if (node->id == "ff" && node->args.size() == 2)
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if (node->id == "ff" && node->args.size() == 2)
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create_ff(module, node);
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create_ff(module, node);
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if (node->id == "latch" && node->args.size() == 2)
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if (node->id == "latch" && node->args.size() == 2)
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create_latch(module, node);
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if (!create_latch(module, node, flag_ignore_miss_data_latch)) {
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delete module;
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goto skip_cell;
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}
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}
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}
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if (node->id == "pin" && node->args.size() == 1)
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if (node->id == "pin" && node->args.size() == 1)
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