From 0470cbb00d82730fd310eb870d8988af840fc150 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Fri, 12 Jan 2024 16:30:37 +0100 Subject: [PATCH] hierarchy: Without a known top module, derive all deferred modules This fixes hierarchy when used with cell libraries that were loaded with -defer and also makes more of the hierarchy visible to the auto-top heuristic. --- passes/hierarchy/hierarchy.cc | 12 ++++++++++++ tests/verilog/param_no_default.ys | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 90f890e80..6fcda5d76 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -1006,6 +1006,18 @@ struct HierarchyPass : public Pass { if (mod->get_bool_attribute(ID::top)) top_mod = mod; + if (top_mod == nullptr) + { + std::vector abstract_ids; + for (auto module : design->modules()) + if (module->name.begins_with("$abstract")) + abstract_ids.push_back(module->name); + for (auto abstract_id : abstract_ids) + design->module(abstract_id)->derive(design, {}); + for (auto abstract_id : abstract_ids) + design->remove(design->module(abstract_id)); + } + if (top_mod == nullptr && auto_top_mode) { log_header(design, "Finding top of design hierarchy..\n"); dict db; diff --git a/tests/verilog/param_no_default.ys b/tests/verilog/param_no_default.ys index cc34c6a53..0509f6a1a 100644 --- a/tests/verilog/param_no_default.ys +++ b/tests/verilog/param_no_default.ys @@ -1,5 +1,5 @@ read_verilog -sv param_no_default.sv -hierarchy +hierarchy -top top proc flatten opt -full