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Added ice40 SB_IO sim model

This commit is contained in:
Clifford Wolf 2015-05-23 09:30:24 +02:00
parent 98bceed0da
commit 264eb8eb6e
1 changed files with 46 additions and 1 deletions
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47
techlibs/ice40/cells_sim.v
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@ -18,7 +18,52 @@ module SB_IO (
parameter [0:0] NEG_TRIGGER = 1'b0; parameter [0:0] NEG_TRIGGER = 1'b0;
parameter IO_STANDARD = "SB_LVCMOS"; parameter IO_STANDARD = "SB_LVCMOS";
/* TBD */ reg din_q_0;
reg din_q_1;
reg dout_q_0;
reg dout_q_1;
reg outena_q;
generate if (!NEG_TRIGGER) begin
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
end else begin
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
end endgenerate
reg outena, dout, din_0, din_1;
always @* begin
if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
din_1 = din_q_1;
end
always @* begin
if (PIN_TYPE[3])
dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
else
dout = (OUTPUT_CLK ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
end
always @* begin
case (PIN_TYPE[5:4])
2'b00: outena = 0;
2'b01: outena = 1;
2'b10: outena = outena_q;
2'b11: outena = OUTPUT_ENABLE;
endcase
end
assign D_IN_0 = din_0, D_IN_1 = din_1;
assign PACKAGE_PIN = outena ? dout : 1'bz;
endmodule endmodule
module SB_GB_IO ( module SB_GB_IO (