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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3

This commit is contained in:
Clifford Wolf 2014-07-23 09:00:16 +02:00
parent c61467a32c
commit 260c19ec5a
4 changed files with 45 additions and 7 deletions
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32
kernel/rtlil.cc
View File

@ -1324,6 +1324,13 @@ RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
offset = 0; offset = 0;
} }
RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
{
this->wire = wire;
this->width = wire->width;
this->offset = 0;
}
RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int width, int offset) RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int width, int offset)
{ {
this->wire = wire; this->wire = wire;
@ -1331,6 +1338,15 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int width, int offset)
this->offset = offset; this->offset = offset;
} }
RTLIL::SigChunk RTLIL::SigChunk::grml(RTLIL::Wire *wire, int offset, int width)
{
RTLIL::SigChunk chunk;
chunk.wire = wire;
chunk.width = width;
chunk.offset = offset;
return chunk;
}
RTLIL::SigChunk::SigChunk(const std::string &str) RTLIL::SigChunk::SigChunk(const std::string &str)
{ {
wire = NULL; wire = NULL;
@ -1432,6 +1448,13 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
check(); check();
} }
RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
{
chunks_.push_back(RTLIL::SigChunk(wire));
width_ = chunks_.back().width;
check();
}
RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset) RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset)
{ {
chunks_.push_back(RTLIL::SigChunk(wire, width, offset)); chunks_.push_back(RTLIL::SigChunk(wire, width, offset));
@ -1439,6 +1462,15 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset)
check(); check();
} }
RTLIL::SigSpec RTLIL::SigSpec::grml(RTLIL::Wire *wire, int offset, int width)
{
RTLIL::SigSpec sig;
sig.chunks_.push_back(RTLIL::SigChunk::grml(wire, offset, width));
sig.width_ = sig.chunks_.back().width;
sig.check();
return sig;
}
RTLIL::SigSpec::SigSpec(const std::string &str) RTLIL::SigSpec::SigSpec(const std::string &str)
{ {
chunks_.push_back(RTLIL::SigChunk(str)); chunks_.push_back(RTLIL::SigChunk(str));

10
kernel/rtlil.h
View File

@ -462,7 +462,10 @@ struct RTLIL::SigChunk {
int width, offset; int width, offset;
SigChunk(); SigChunk();
SigChunk(const RTLIL::Const &value); SigChunk(const RTLIL::Const &value);
SigChunk(RTLIL::Wire *wire, int width, int offset); SigChunk(RTLIL::Wire *wire);
SigChunk(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error
SigChunk(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated));
static SigChunk grml(RTLIL::Wire *wire, int offset, int width = 1);
SigChunk(const std::string &str); SigChunk(const std::string &str);
SigChunk(int val, int width = 32); SigChunk(int val, int width = 32);
SigChunk(RTLIL::State bit, int width = 1); SigChunk(RTLIL::State bit, int width = 1);
@ -522,7 +525,10 @@ public:
SigSpec(); SigSpec();
SigSpec(const RTLIL::Const &value); SigSpec(const RTLIL::Const &value);
SigSpec(const RTLIL::SigChunk &chunk); SigSpec(const RTLIL::SigChunk &chunk);
SigSpec(RTLIL::Wire *wire, int width = -1, int offset = 0); SigSpec(RTLIL::Wire *wire);
SigSpec(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error
SigSpec(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated));
static SigSpec grml(RTLIL::Wire *wire, int offset, int width = 1);
SigSpec(const std::string &str); SigSpec(const std::string &str);
SigSpec(int val, int width = 32); SigSpec(int val, int width = 32);
SigSpec(RTLIL::State bit, int width = 1); SigSpec(RTLIL::State bit, int width = 1);

2
passes/abc/abc.cc
View File

@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
clk_str = clk_str.substr(1); clk_str = clk_str.substr(1);
} }
if (module->wires.count(RTLIL::escape_id(clk_str)) != 0) if (module->wires.count(RTLIL::escape_id(clk_str)) != 0)
clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1)); clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1, 0));
} }
if (dff_mode && clk_sig.size() == 0) if (dff_mode && clk_sig.size() == 0)

8
passes/sat/share.cc
View File

@ -292,8 +292,8 @@ struct ShareWorker
supercell->connections["\\Y"] = y; supercell->connections["\\Y"] = y;
module->add(supercell); module->add(supercell);
RTLIL::SigSpec new_y1(y, y1.size()); RTLIL::SigSpec new_y1(y, y1.size(), 0);
RTLIL::SigSpec new_y2(y, y2.size()); RTLIL::SigSpec new_y2(y, y2.size(), 0);
module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2)); module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@ -405,8 +405,8 @@ struct ShareWorker
supercell->connections["\\Y"] = y; supercell->connections["\\Y"] = y;
supercell->check(); supercell->check();
RTLIL::SigSpec new_y1(y, y1.size()); RTLIL::SigSpec new_y1(y, y1.size(), 0);
RTLIL::SigSpec new_y2(y, y2.size()); RTLIL::SigSpec new_y2(y, y2.size(), 0);
module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2)); module->connections.push_back(RTLIL::SigSig(y2, new_y2));