mirror of https://github.com/YosysHQ/yosys.git
Updating the intro
Based on the Ignite presentation and github. Adds links for the extended Yosys universe. Moves the original thesis stuff further down (and labels it as such).
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Krystine Sherwin
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What is Yosys
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=============
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.. todo:: rewrite to not be a thesis abstract
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Yosys began as a BSc thesis project by Claire Wolf intended to support synthesis
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for a CGRA (coarse-grained reconfigurable architecture). It then expanded into
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more general infrastructure for research on synthesis.
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:Abstract:
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Most of today's digital design is done in HDL code (mostly Verilog or
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VHDL) and with the help of HDL synthesis tools.
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Modern Yosys has full support for the synthesizable subset of Verilog-2005 and
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has been described as "the GCC of hardware synthesis." Freely available and
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`open source`_, Yosys finds use across hobbyist and commercial applications as well
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as academic.
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In special cases such as synthesis for coarse-grain cell libraries or
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when testing new synthesis algorithms it might be necessary to write a
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custom HDL synthesis tool or add new features to an existing one. In
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these cases the availability of a Free and Open Source (FOSS) synthesis
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tool that can be used as basis for custom tools would be helpful.
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.. _open source: https://github.com/YosysHQ/yosys
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In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys)
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was developed. This document covers the design and implementation of
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this tool. At the moment the main focus of Yosys lies on the high-level
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aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool
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ABC is used by Yosys to perform advanced gate-level optimizations.
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.. note:: Yosys is released under the ISC License:
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An evaluation of Yosys based on real-world designs is included. It is
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shown that Yosys can be used as-is to synthesize such designs. The
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results produced by Yosys in this tests where successfully verified
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using formal verification and are comparable in quality to the results
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produced by a commercial synthesis tool.
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A permissive license lets people do anything with your code with proper
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attribution and without warranty. The ISC license is functionally equivalent
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to the BSD 2-Clause and MIT licenses, removing some language that is no
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longer necessary.
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This document was originally published as bachelor thesis at the Vienna
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University of Technology :cite:p:`BACC`.
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Together with the place and route tool `nextpnr`_, Yosys can be used to program
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some FPGAs with a fully end-to-end open source flow (Lattice iCE40 and ECP5). It
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also does the synthesis portion for the `OpenLane flow`_, targeting the SkyWater
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130nm open source PDK for fully open source ASIC design. Yosys can also do
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formal verification with backends for solver formats like `SMT2`_.
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Yosys is a Verilog HDL synthesis tool. This means that it takes a behavioural
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design description as input and generates an RTL, logical gate or physical gate
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level description of the design as output. Yosys' main strengths are behavioural
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and RTL synthesis. A wide range of commands (synthesis passes) exist within
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Yosys that can be used to perform a wide range of synthesis tasks within the
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domain of behavioural, rtl and logic synthesis. Yosys is designed to be
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extensible and therefore is a good basis for implementing custom synthesis tools
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for specialised tasks.
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.. _nextpnr: https://github.com/YosysHQ/nextpnr
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.. _OpenLane flow: https://github.com/The-OpenROAD-Project/OpenLane
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.. _SMT2: https://smtlib.cs.uiowa.edu/
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.. figure:: /_images/primer/levels_of_abstraction.*
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Yosys, and the accompanying Open Source EDA ecosystem, is currently maintained
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by `Yosys Headquarters`_, with many of the core developers employed by `YosysHQ
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GmbH`_. A commercial extension, `Tabby CAD Suite`_, includes the Verific
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frontend for industry-grade SystemVerilog and VHDL support, formal verification
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with SVA, and formal apps.
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.. _Yosys Headquarters: https://github.com/YosysHQ
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.. _YosysHQ GmbH: https://www.yosyshq.com/about
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.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
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.. figure:: /_static/logo.png
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:class: width-helper
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:name: fig:Levels_of_abstraction
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Where Yosys exists in the layers of abstraction
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What you can do with Yosys
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--------------------------
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@ -72,8 +71,71 @@ Things you can't do
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.. _nextpnr: https://github.com/YosysHQ/nextpnr
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The extended Yosys universe
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---------------------------
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In no particular order:
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- SBY for formal verification
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- https://github.com/YosysHQ/sby
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- https://yosyshq.readthedocs.io/projects/sby
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- EQY for equivalence checking
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- https://github.com/YosysHQ/eqy
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- https://yosyshq.readthedocs.io/projects/eqy
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- MCY for mutation coverage
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- https://github.com/YosysHQ/mcy
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- https://yosyshq.readthedocs.io/projects/mcy
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- SCY for deep formal traces
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- https://github.com/YosysHQ/scy
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The original thesis abstract
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----------------------------
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The first version of the Yosys documentation was published as a bachelor thesis
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at the Vienna University of Technology :cite:p:`BACC`.
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:Abstract:
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Most of today's digital design is done in HDL code (mostly Verilog or
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VHDL) and with the help of HDL synthesis tools.
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In special cases such as synthesis for coarse-grain cell libraries or
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when testing new synthesis algorithms it might be necessary to write a
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custom HDL synthesis tool or add new features to an existing one. In
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these cases the availability of a Free and Open Source (FOSS) synthesis
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tool that can be used as basis for custom tools would be helpful.
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In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys)
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was developed. This document covers the design and implementation of
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this tool. At the moment the main focus of Yosys lies on the high-level
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aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool
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ABC is used by Yosys to perform advanced gate-level optimizations.
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An evaluation of Yosys based on real-world designs is included. It is
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shown that Yosys can be used as-is to synthesize such designs. The
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results produced by Yosys in this tests where successfully verified
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using formal verification and are comparable in quality to the results
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produced by a commercial synthesis tool.
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Yosys is a Verilog HDL synthesis tool. This means that it takes a behavioural
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design description as input and generates an RTL, logical gate or physical gate
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level description of the design as output. Yosys' main strengths are behavioural
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and RTL synthesis. A wide range of commands (synthesis passes) exist within
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Yosys that can be used to perform a wide range of synthesis tasks within the
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domain of behavioural, rtl and logic synthesis. Yosys is designed to be
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extensible and therefore is a good basis for implementing custom synthesis tools
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for specialised tasks.
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.. figure:: /_images/primer/levels_of_abstraction.*
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:class: width-helper
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:name: fig:Levels_of_abstraction
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Where Yosys exists in the layers of abstraction
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Benefits of open source HDL synthesis
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-------------------------------------
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Cost (also applies to ``free as in free beer`` solutions):
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@ -114,30 +176,10 @@ Benefits of open source HDL synthesis
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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The extended Yosys universe
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---------------------------
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In no particular order:
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- SBY for formal verification
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- https://github.com/YosysHQ/sby
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- https://yosyshq.readthedocs.io/projects/sby
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- EQY for equivalence checking
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- https://github.com/YosysHQ/eqy
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- https://yosyshq.readthedocs.io/projects/eqy
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- MCY for mutation coverage
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- https://github.com/YosysHQ/mcy
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- https://yosyshq.readthedocs.io/projects/mcy
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- SCY for deep formal traces
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- https://github.com/YosysHQ/scy
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History of Yosys
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----------------
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~~~~~~~~~~~~~~~~
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.. todo:: make less academic
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.. todo:: Consider a less academic version of the History of Yosys
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A Hardware Description Language (HDL) is a computer language used to describe
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circuits. A HDL synthesis tool is a computer program that takes a formal
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