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Merge pull request #570 from edcote/patch-4 

Include module name for area summary stats
This commit is contained in:
Clifford Wolf 2018-06-19 13:47:39 +02:00 committed by GitHub
parent 0ff0ce4973 d89560a0ba
commit 25c5002f83
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 4 deletions
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8
passes/cmds/stat.cc
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@ -142,7 +142,7 @@ struct statdata_t
} }
} }
void log_data() void log_data(RTLIL::IdString mod_name, bool top_mod)
{ {
log(" Number of wires: %6d\n", num_wires); log(" Number of wires: %6d\n", num_wires);
log(" Number of wire bits: %6d\n", num_wire_bits); log(" Number of wire bits: %6d\n", num_wire_bits);
@ -163,7 +163,7 @@ struct statdata_t
if (area != 0) { if (area != 0) {
log("\n"); log("\n");
log(" Chip area for this module: %f\n", area); log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
} }
} }
}; };
@ -275,7 +275,7 @@ struct StatPass : public Pass {
log("\n"); log("\n");
log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)"); log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)");
log("\n"); log("\n");
data.log_data(); data.log_data(mod->name, false);
} }
if (top_mod != NULL && GetSize(mod_stat) > 1) if (top_mod != NULL && GetSize(mod_stat) > 1)
@ -288,7 +288,7 @@ struct StatPass : public Pass {
statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0); statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0);
log("\n"); log("\n");
data.log_data(); data.log_data(top_mod->name, true);
} }
log("\n"); log("\n");