mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #761 from whitequark/proc_clean_partial
proc_clean: remove any empty cases, if possible to do safely
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commit
245724a504
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@ -3793,6 +3793,11 @@ RTLIL::CaseRule::~CaseRule()
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delete *it;
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}
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bool RTLIL::CaseRule::empty() const
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{
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return actions.empty() && switches.empty();
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}
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RTLIL::CaseRule *RTLIL::CaseRule::clone() const
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{
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RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
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@ -3809,6 +3814,11 @@ RTLIL::SwitchRule::~SwitchRule()
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delete *it;
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}
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bool RTLIL::SwitchRule::empty() const
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{
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return cases.empty();
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}
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RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
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{
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RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
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@ -1227,6 +1227,8 @@ struct RTLIL::CaseRule
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~CaseRule();
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void optimize();
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bool empty() const;
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template<typename T> void rewrite_sigspecs(T &functor);
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RTLIL::CaseRule *clone() const;
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};
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@ -1238,6 +1240,8 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject
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~SwitchRule();
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bool empty() const;
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template<typename T> void rewrite_sigspecs(T &functor);
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RTLIL::SwitchRule *clone() const;
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};
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@ -77,18 +77,36 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
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}
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else
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{
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bool all_cases_are_empty = true;
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for (auto cs : sw->cases) {
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if (cs->actions.size() != 0 || cs->switches.size() != 0)
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all_cases_are_empty = false;
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bool all_fully_def = true;
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for (auto cs : sw->cases)
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{
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if (max_depth != 0)
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proc_clean_case(cs, did_something, count, max_depth-1);
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for (auto cmp : cs->compare)
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if (!cmp.is_fully_def())
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all_fully_def = false;
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}
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if (all_cases_are_empty) {
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if (all_fully_def)
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{
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for (auto cs = sw->cases.begin(); cs != sw->cases.end();)
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{
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if ((*cs)->empty())
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{
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did_something = true;
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for (auto cs : sw->cases)
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delete cs;
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sw->cases.clear();
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delete *cs;
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cs = sw->cases.erase(cs);
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}
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else ++cs;
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}
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}
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else
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{
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while (!sw->cases.empty() && sw->cases.back()->empty())
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{
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did_something = true;
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delete sw->cases.back();
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sw->cases.pop_back();
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}
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}
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}
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}
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@ -106,7 +124,7 @@ void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int m
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}
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for (size_t i = 0; i < cs->switches.size(); i++) {
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RTLIL::SwitchRule *sw = cs->switches[i];
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if (sw->cases.size() == 0) {
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if (sw->empty()) {
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cs->switches.erase(cs->switches.begin() + (i--));
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did_something = true;
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delete sw;
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