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Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays

This commit is contained in:
Clifford Wolf 2019-06-20 12:03:00 +02:00
parent 3b1e5264d8 8b8af10f5e
commit 2428fb7dc2
3 changed files with 13 additions and 1 deletions
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8
frontends/verilog/verilog_parser.y
View File

@ -1400,7 +1400,13 @@ wire_name:
node->children.push_back(rng); node->children.push_back(rng);
} }
node->type = AST_MEMORY; node->type = AST_MEMORY;
node->children.push_back($2); auto *rangeNode = $2;
if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
// SV array size [n], rewrite as [n-1:0]
rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
rangeNode->children.push_back(AstNode::mkconst_int(0, false));
}
node->children.push_back(rangeNode);
} }
if (current_function_or_task == NULL) { if (current_function_or_task == NULL) {
if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) { if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {

4
tests/various/unpacked_arrays.sv Normal file
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@ -0,0 +1,4 @@
module unpacked_arrays;
reg array_range [0:7];
reg array_size [8];
endmodule

2
tests/various/unpacked_arrays.ys Normal file
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@ -0,0 +1,2 @@
read_verilog -sv unpacked_arrays.sv
stat