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Add arrival times for HX devices

This commit is contained in:
Eddie Hung 2019-08-28 17:21:37 -07:00
parent e4f89e01b5
commit 2421cb3fed
1 changed files with 114 additions and 21 deletions
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135
techlibs/ice40/cells_sim.v
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@ -2,6 +2,10 @@
`define SB_DFF_REG reg Q = 0 `define SB_DFF_REG reg Q = 0
// `define SB_DFF_REG reg Q // `define SB_DFF_REG reg Q
`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif
`define ABC_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc_arrival=TIME *) `endif
// SiliconBlue IO Cells // SiliconBlue IO Cells
module SB_IO ( module SB_IO (
@ -169,20 +173,34 @@ module \$__ICE40_CARRY_WRAPPER (
); );
endmodule endmodule
// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
// Positive Edge SiliconBlue FF Cells // Positive Edge SiliconBlue FF Cells
module SB_DFF (output `SB_DFF_REG, input C, D); module SB_DFF (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, D
);
always @(posedge C) always @(posedge C)
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFE (output `SB_DFF_REG, input C, E, D); module SB_DFFE (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, E, D
);
always @(posedge C) always @(posedge C)
if (E) if (E)
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFSR (output `SB_DFF_REG, input C, R, D); module SB_DFFSR (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, R, D
);
always @(posedge C) always @(posedge C)
if (R) if (R)
Q <= 0; Q <= 0;
@ -190,7 +208,11 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFR (output `SB_DFF_REG, input C, R, D); module SB_DFFR (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, R, D
);
always @(posedge C, posedge R) always @(posedge C, posedge R)
if (R) if (R)
Q <= 0; Q <= 0;
@ -198,7 +220,11 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFSS (output `SB_DFF_REG, input C, S, D); module SB_DFFSS (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, S, D
);
always @(posedge C) always @(posedge C)
if (S) if (S)
Q <= 1; Q <= 1;
@ -206,7 +232,11 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFS (output `SB_DFF_REG, input C, S, D); module SB_DFFS (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, S, D
);
always @(posedge C, posedge S) always @(posedge C, posedge S)
if (S) if (S)
Q <= 1; Q <= 1;
@ -214,7 +244,11 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D); module SB_DFFESR (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, E, R, D
);
always @(posedge C) always @(posedge C)
if (E) begin if (E) begin
if (R) if (R)
@ -224,7 +258,11 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
end end
endmodule endmodule
module SB_DFFER (output `SB_DFF_REG, input C, E, R, D); module SB_DFFER (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, E, R, D
);
always @(posedge C, posedge R) always @(posedge C, posedge R)
if (R) if (R)
Q <= 0; Q <= 0;
@ -232,7 +270,11 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D); module SB_DFFESS (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, E, S, D
);
always @(posedge C) always @(posedge C)
if (E) begin if (E) begin
if (S) if (S)
@ -242,7 +284,11 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
end end
endmodule endmodule
module SB_DFFES (output `SB_DFF_REG, input C, E, S, D); module SB_DFFES (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, E, S, D
);
always @(posedge C, posedge S) always @(posedge C, posedge S)
if (S) if (S)
Q <= 1; Q <= 1;
@ -252,18 +298,30 @@ endmodule
// Negative Edge SiliconBlue FF Cells // Negative Edge SiliconBlue FF Cells
module SB_DFFN (output `SB_DFF_REG, input C, D); module SB_DFFN (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, D
);
always @(negedge C) always @(negedge C)
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNE (output `SB_DFF_REG, input C, E, D); module SB_DFFNE (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, E, D
);
always @(negedge C) always @(negedge C)
if (E) if (E)
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNSR (output `SB_DFF_REG, input C, R, D); module SB_DFFNSR (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, R, D
);
always @(negedge C) always @(negedge C)
if (R) if (R)
Q <= 0; Q <= 0;
@ -271,7 +329,11 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNR (output `SB_DFF_REG, input C, R, D); module SB_DFFNR (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, R, D
);
always @(negedge C, posedge R) always @(negedge C, posedge R)
if (R) if (R)
Q <= 0; Q <= 0;
@ -279,7 +341,11 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNSS (output `SB_DFF_REG, input C, S, D); module SB_DFFNSS (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, S, D
);
always @(negedge C) always @(negedge C)
if (S) if (S)
Q <= 1; Q <= 1;
@ -287,7 +353,11 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNS (output `SB_DFF_REG, input C, S, D); module SB_DFFNS (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, S, D
);
always @(negedge C, posedge S) always @(negedge C, posedge S)
if (S) if (S)
Q <= 1; Q <= 1;
@ -295,7 +365,11 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D); module SB_DFFNESR (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, E, R, D
);
always @(negedge C) always @(negedge C)
if (E) begin if (E) begin
if (R) if (R)
@ -305,7 +379,11 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
end end
endmodule endmodule
module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D); module SB_DFFNER (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, E, R, D
);
always @(negedge C, posedge R) always @(negedge C, posedge R)
if (R) if (R)
Q <= 0; Q <= 0;
@ -313,7 +391,11 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
Q <= D; Q <= D;
endmodule endmodule
module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D); module SB_DFFNESS (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, E, S, D
);
always @(negedge C) always @(negedge C)
if (E) begin if (E) begin
if (S) if (S)
@ -323,7 +405,11 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
end end
endmodule endmodule
module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D); module SB_DFFNES (
`ABC_ARRIVAL_HX(540)
output `SB_DFF_REG,
input C, E, S, D
);
always @(negedge C, posedge S) always @(negedge C, posedge S)
if (S) if (S)
Q <= 1; Q <= 1;
@ -334,6 +420,7 @@ endmodule
// SiliconBlue RAM Cells // SiliconBlue RAM Cells
module SB_RAM40_4K ( module SB_RAM40_4K (
`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
output [15:0] RDATA, output [15:0] RDATA,
input RCLK, RCLKE, RE, input RCLK, RCLKE, RE,
input [10:0] RADDR, input [10:0] RADDR,
@ -502,6 +589,7 @@ module SB_RAM40_4K (
endmodule endmodule
module SB_RAM40_4KNR ( module SB_RAM40_4KNR (
`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
output [15:0] RDATA, output [15:0] RDATA,
input RCLKN, RCLKE, RE, input RCLKN, RCLKE, RE,
input [10:0] RADDR, input [10:0] RADDR,
@ -567,6 +655,7 @@ module SB_RAM40_4KNR (
endmodule endmodule
module SB_RAM40_4KNW ( module SB_RAM40_4KNW (
`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
output [15:0] RDATA, output [15:0] RDATA,
input RCLK, RCLKE, RE, input RCLK, RCLKE, RE,
input [10:0] RADDR, input [10:0] RADDR,
@ -632,6 +721,7 @@ module SB_RAM40_4KNW (
endmodule endmodule
module SB_RAM40_4KNRNW ( module SB_RAM40_4KNRNW (
`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
output [15:0] RDATA, output [15:0] RDATA,
input RCLKN, RCLKE, RE, input RCLKN, RCLKE, RE,
input [10:0] RADDR, input [10:0] RADDR,
@ -700,7 +790,10 @@ endmodule
module ICESTORM_LC ( module ICESTORM_LC (
input I0, I1, I2, I3, CIN, CLK, CEN, SR, input I0, I1, I2, I3, CIN, CLK, CEN, SR,
output LO, O, COUT output LO,
`ABC_ARRIVAL_HX(540)
output O,
output COUT
); );
parameter [15:0] LUT_INIT = 0; parameter [15:0] LUT_INIT = 0;