mirror of https://github.com/YosysHQ/yosys.git
Fix $anyseq warning and cleanup
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parent
8fd455c910
commit
23cd2e5de0
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@ -252,7 +252,7 @@ struct XAigerWriter
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RTLIL::Module* box_module = module->design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc_box_id")) {
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for (const auto &c : cell->connections()) {
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/*if (c.second.is_fully_const()) continue;*/
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if (c.second.is_fully_const()) continue;
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for (auto b : c.second.bits()) {
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Wire *w = b.wire;
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if (!w) continue;
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@ -271,8 +271,7 @@ struct XAigerWriter
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if (is_output) {
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SigBit O = sigmap(b);
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input_bits.insert(O);
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if (!O.wire->port_output)
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undriven_bits.erase(O);
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undriven_bits.erase(O);
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}
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}
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}
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@ -312,24 +311,19 @@ struct XAigerWriter
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cell->connections_.sort(RTLIL::sort_by_id_str());
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for (const auto &c : cell->connections()) {
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/*if (c.second.is_fully_const()) continue;*/
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for (auto b : c.second.bits()) {
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auto is_input = cell->input(c.first);
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auto is_output = cell->output(c.first);
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log_assert(is_input || is_output);
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if (is_input) {
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/*if (!w->port_input)*/ {
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SigBit I = sigmap(b);
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if (I != b)
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alias_map[b] = I;
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/*if (!output_bits.count(b))*/
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co_bits.emplace_back(b, 0);
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}
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SigBit I = sigmap(b);
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if (I != b)
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alias_map[b] = I;
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co_bits.emplace_back(b, 0);
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}
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if (is_output) {
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SigBit O = sigmap(b);
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/*if (!input_bits.count(O))*/
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ci_bits.emplace_back(O, 0);
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ci_bits.emplace_back(O, 0);
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}
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}
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}
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@ -367,9 +361,6 @@ struct XAigerWriter
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//co_bits.erase(bit);
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output_bits.erase(bit);
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}
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// Erase all CIs that are also COs
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//for (auto bit : co_bits)
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// ci_bits.erase(bit);
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// CIs cannot be undriven
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for (const auto &c : ci_bits)
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undriven_bits.erase(c.first);
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