diff --git a/tests/various/tcl_apis.tcl b/tests/various/tcl_apis.tcl
new file mode 100644
index 000000000..74f1aaa52
--- /dev/null
+++ b/tests/various/tcl_apis.tcl
@@ -0,0 +1,16 @@
+yosys read_verilog tcl_apis.v
+
+if {[rtlil::get_attr -string -mod top foo] != "bar"} {
+	error "bad top module attribute"
+}
+
+if {[rtlil::get_attr -bool top w dont_touch] != 1} {
+	error "bad w wire attribute"
+}
+
+if {[rtlil::get_param -int top inst PARAM] != 4} {
+	error "bad parameter"
+}
+
+rtlil::set_attr -true -mod top marked
+yosys select -assert-any A:marked
diff --git a/tests/various/tcl_apis.v b/tests/various/tcl_apis.v
new file mode 100644
index 000000000..cc379c20a
--- /dev/null
+++ b/tests/various/tcl_apis.v
@@ -0,0 +1,11 @@
+module m;
+parameter PARAM = 0;
+endmodule
+
+(* foo="bar" *)
+module top;
+	(* dont_touch *)
+	wire w;
+
+	m #(.PARAM(4)) inst();
+endmodule
diff --git a/tests/various/tcl_apis.ys b/tests/various/tcl_apis.ys
new file mode 100644
index 000000000..141f08a3b
--- /dev/null
+++ b/tests/various/tcl_apis.ys
@@ -0,0 +1 @@
+yosys tcl tcl_apis.tcl