riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added CARRY4 Xilinx cell to xsthammer cell lib

This commit is contained in:
Clifford Wolf 2013-07-05 14:46:33 +02:00
parent 45105faf25
commit 238ff14810
1 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
tests/xsthammer/xl_cells.v
View File

@ -99,3 +99,16 @@ output O;
assign O = CI ^ LI; assign O = CI ^ LI;
endmodule endmodule
module CARRY4(CO, O, CI, CYINIT, DI, S);
output [3:0] CO, O;
input CI, CYINIT;
input [3:0] DI, S;
wire ci_or_cyinit;
assign O = S ^ {CO[2:0], ci_or_cyinit};
assign CO[0] = S[0] ? ci_or_cyinit : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1];
assign CO[2] = S[2] ? CO[1] : DI[2];
assign CO[3] = S[3] ? CO[2] : DI[3];
assign ci_or_cyinit = CI | CYINIT;
endmodule