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Do not treat $__ABC_FF_ as a user cell

This commit is contained in:
Eddie Hung 2019-06-15 19:36:55 -07:00
parent 9ec57b46c2
commit 2309459605
2 changed files with 15 additions and 30 deletions
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18
backends/aiger/xaiger.cc
View File

@ -222,15 +222,15 @@ struct XAigerWriter
log_assert(!holes_mode);
// FIXME: Should short here, rather than provide $__ABC_FF_
// to ABC like a user cell
//if (cell->type == "$__ABC_FF_")
//{
// SigBit D = sigmap(cell->getPort("\\D").as_bit());
// SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
// alias_map[Q] = D;
// continue;
//}
if (cell->type == "$__ABC_FF_")
{
SigBit D = sigmap(cell->getPort("\\D").as_bit());
SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
unused_bits.erase(D);
undriven_bits.erase(Q);
alias_map[Q] = D;
continue;
}
RTLIL::Module* inst_module = !holes_mode ? module->design->module(cell->type) : nullptr;
bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;

17
passes/techmap/abc9.cc
View File

@ -512,27 +512,19 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
}
// Remove all AND, NOT, and ABC box instances
// in preparation for stitching mapped_mod in
// Short $_FF_ cells used by ABC (FIXME)
dict<IdString, decltype(RTLIL::Cell::parameters)> erased_boxes;
std::vector<RTLIL::Cell*> abc_dff;
for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
RTLIL::Cell* cell = it->second;
if (cell->type.in("$_AND_", "$_NOT_")) {
if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) {
it = module->cells_.erase(it);
continue;
}
if (cell->type.in("$__ABC_FF_"))
abc_dff.emplace_back(cell);
else {
RTLIL::Module* box_module = design->module(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id")) {
erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters)));
it = module->cells_.erase(it);
continue;
}
}
++it;
}
// Do the same for module connections
@ -695,13 +687,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
}
for (auto cell : abc_dff) {
RTLIL::SigBit D = cell->getPort("\\D");
RTLIL::SigBit Q = cell->getPort("\\Q");
module->connect(Q, D);
module->remove(cell);
}
//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
log("ABC RESULTS: input signals: %8d\n", in_wires);
log("ABC RESULTS: output signals: %8d\n", out_wires);