mirror of https://github.com/YosysHQ/yosys.git
Added "add" command (only wires for now)
This commit is contained in:
Clifford Wolf
parent
65ad556f3d
commit
2279b2a196
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@ -1,4 +1,5 @@
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OBJS += passes/cmds/add.o
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OBJS += passes/cmds/design.o
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OBJS += passes/cmds/select.o
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OBJS += passes/cmds/show.o
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@ -0,0 +1,154 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
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{
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name = RTLIL::escape_id(name);
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if (module->count_id(name) != 0)
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{
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RTLIL::Wire *wire = NULL;
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if (module->wires.count(name) > 0)
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wire = module->wires.at(name);
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if (wire != NULL && wire->width != width)
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wire = NULL;
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if (wire != NULL && wire->port_input != flag_input)
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wire = NULL;
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if (wire != NULL && wire->port_output != flag_output)
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wire = NULL;
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if (wire == NULL)
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log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
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log("Skipping module %s as it already has such an object.\n", module->name.c_str());
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return;
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}
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->name = name;
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wire->width = width;
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wire->port_input = flag_input;
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wire->port_output = flag_output;
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module->add(wire);
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if (flag_input || flag_output) {
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wire->port_id = module->wires.size();
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module->fixup_ports();
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}
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log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
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if (!flag_global)
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return;
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for (auto &it : module->cells)
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{
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if (design->modules.count(it.second->type) == 0)
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continue;
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RTLIL::Module *mod = design->modules.at(it.second->type);
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if (!design->selected_whole_module(mod->name))
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continue;
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if (mod->get_bool_attribute("\\placeholder"))
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continue;
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if (it.second->connections.count(name) > 0)
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continue;
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it.second->connections[name] = wire;
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log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
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}
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}
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struct AddPass : public Pass {
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AddPass() : Pass("add", "add objects to the design") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" add <command> [selection]\n");
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log("\n");
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log("This command adds objects to the design. It operates on all fully selected\n");
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log("modules. So e.g. 'add -wire foo' will add a wire foo to all selected modules.\n");
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log("\n");
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log("\n");
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log(" add {-wire|-input|-inout|-output} <name> <width> [selection]\n");
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log("\n");
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log("Add a wire (input, inout, output port) with the given name and width. The\n");
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log("command will fail if the object exists already and has different properties\n");
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log("than the object to be created.\n");
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log("\n");
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log("\n");
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log(" add -global_input <name> <width> [selection]\n");
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log("\n");
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log("Like 'add -input', but also connect the signal between instances of the\n");
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log("selected modules.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string command;
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std::string arg_name;
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bool arg_flag_input = false;
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bool arg_flag_output = false;
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bool arg_flag_global = false;
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int arg_width = 0;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-wire" || arg == "-input" || arg == "-inout" || arg == "-output" || arg == "-global_input") {
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if (argidx+2 >= args.size())
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break;
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command = "wire";
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if (arg == "-input" || arg == "-inout" || arg == "-global_input")
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arg_flag_input = true;
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if (arg == "-output" || arg == "-inout")
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arg_flag_output = true;
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if (arg == "-global_input")
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arg_flag_global = true;
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arg_name = args[++argidx];
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arg_width = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto &mod : design->modules)
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{
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RTLIL::Module *module = mod.second;
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if (!design->selected_whole_module(module->name))
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continue;
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if (module->get_bool_attribute("\\placeholder"))
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continue;
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if (command == "wire")
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add_wire(design, module, arg_name, arg_width, arg_flag_input, arg_flag_output, arg_flag_global);
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}
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}
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} AddPass;
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