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fix tests not expecting ioffs

This commit is contained in:
N. Engelhardt 2025-01-24 21:29:10 +01:00
parent 1cf8e7c7db
commit 2241a65f78
2 changed files with 3 additions and 3 deletions
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2
tests/arch/quicklogic/qlf_k6n10f/counter.ys
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@ -2,7 +2,7 @@ read_verilog ../../common/counter.v
hierarchy -top top hierarchy -top top
proc proc
flatten flatten
equiv_opt -assert -multiclock -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check equiv_opt -assert -multiclock -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f -noioff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 4 t:$lut select -assert-count 4 t:$lut

4
tests/arch/quicklogic/qlf_k6n10f/dffs.ys
View File

@ -5,7 +5,7 @@ design -save read
hierarchy -top my_dff hierarchy -top my_dff
proc proc
equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f -noioff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd my_dff # Constrain all select calls below inside the top module cd my_dff # Constrain all select calls below inside the top module
select -assert-count 1 t:sdffsre select -assert-count 1 t:sdffsre
@ -14,7 +14,7 @@ select -assert-none t:sdffsre %% t:* %D
design -load read design -load read
hierarchy -top my_dffe hierarchy -top my_dffe
proc proc
equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f -noioff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd my_dffe # Constrain all select calls below inside the top module cd my_dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:sdffsre select -assert-count 1 t:sdffsre