riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add plus-assignment operator 

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
This commit is contained in:
Kamil Rakoczy 2020-06-03 16:44:02 +02:00
parent 416a66aee8
commit 22408f24c7
2 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
frontends/verilog/verilog_lexer.l
View File

@ -527,6 +527,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
".*" { return TOK_WILDCARD_CONNECT; }
"|=" { SV_KEYWORD(TOK_OR_ASSIGN); }
"+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); }
[-+]?[=*]> {
if (!specify_mode) REJECT;

10
frontends/verilog/verilog_parser.y
View File

@ -256,7 +256,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_OR_ASSIGN TOK_AUTOMATIC
@ -2342,6 +2342,14 @@ simple_behavioral_stmt:
SET_AST_NODE_LOC(node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
} |
attr lvalue TOK_PLUS_ASSIGN delay expr {
AstNode *add_node = new AstNode(AST_ADD, $2->clone(), $5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, add_node);
SET_AST_NODE_LOC(node, @2, @5);
SET_AST_NODE_LOC(add_node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
};
// this production creates the obligatory if-else shift/reduce conflict