mirror of https://github.com/YosysHQ/yosys.git
Add smtbmc support for memory vcd dumping
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@ -550,11 +550,109 @@ def write_vcd_trace(steps_start, steps_stop, index):
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vcd.add_net([topmod] + netpath, smt.net_width(topmod, netpath))
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vcd.add_net([topmod] + netpath, smt.net_width(topmod, netpath))
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path_list.append(netpath)
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path_list.append(netpath)
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mem_trace_data = dict()
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for mempath in sorted(smt.hiermems(topmod)):
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abits, width, rports, wports = smt.mem_info(topmod, mempath)
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expr_id = list()
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expr_list = list()
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for i in range(steps_start, steps_stop):
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for j in range(rports):
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expr_id.append(('R', i-steps_start, j, 'A'))
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expr_id.append(('R', i-steps_start, j, 'D'))
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expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dA" % j))
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expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dD" % j))
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for j in range(wports):
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expr_id.append(('W', i-steps_start, j, 'A'))
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expr_id.append(('W', i-steps_start, j, 'D'))
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expr_id.append(('W', i-steps_start, j, 'M'))
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expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dA" % j))
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expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dD" % j))
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expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dM" % j))
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rdata = list()
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wdata = list()
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addrs = set()
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for eid, edat in zip(expr_id, smt.get_list(expr_list)):
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t, i, j, f = eid
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if t == 'R':
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c = rdata
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elif t == 'W':
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c = wdata
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else:
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assert False
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while len(c) <= i:
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c.append(list())
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c = c[i]
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while len(c) <= j:
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c.append(dict())
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c = c[j]
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c[f] = smt.bv2bin(edat)
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if f == 'A':
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addrs.add(c[f])
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for addr in addrs:
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tdata = list()
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data = ["x"] * width
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gotread = False
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assert len(rdata) == len(wdata)
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for i in range(len(wdata)):
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if not gotread:
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for j_data in rdata[i]:
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if j_data["A"] == addr:
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data = list(j_data["D"])
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gotread = True
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break
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if gotread:
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buf = data[:]
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for i in reversed(range(len(tdata))):
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for k in range(width):
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if tdata[i][k] == "x":
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tdata[i][k] = buf[k]
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else:
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buf[k] = tdata[i][k]
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tdata.append(data[:])
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for j_data in wdata[i]:
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if j_data["A"] != addr:
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continue
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D = j_data["D"]
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M = j_data["M"]
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for k in range(width):
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if M[k] == "1":
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data[k] = D[k]
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assert len(tdata) == len(rdata)
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netpath = mempath[:]
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netpath[-1] += "<%d>" % int(addr, 2)
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vcd.add_net([topmod] + netpath, width)
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for i in range(steps_start, steps_stop):
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if i not in mem_trace_data:
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mem_trace_data[i] = list()
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mem_trace_data[i].append((netpath, "".join(tdata[i-steps_start])))
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for i in range(steps_start, steps_stop):
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for i in range(steps_start, steps_stop):
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vcd.set_time(i)
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vcd.set_time(i)
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value_list = smt.get_net_bin_list(topmod, path_list, "s%d" % i)
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value_list = smt.get_net_bin_list(topmod, path_list, "s%d" % i)
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for path, value in zip(path_list, value_list):
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for path, value in zip(path_list, value_list):
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vcd.set_net([topmod] + path, value)
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vcd.set_net([topmod] + path, value)
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if i in mem_trace_data:
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for path, value in mem_trace_data[i]:
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vcd.set_net([topmod] + path, value)
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vcd.set_time(steps_stop)
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vcd.set_time(steps_stop)
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